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30 lines
1 KiB
Diff
30 lines
1 KiB
Diff
From 80d4cec4cef8282e5ac3aaf98ce3e68fb299a134 Mon Sep 17 00:00:00 2001
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From: Terry Zhou <bjzhou@marvell.com>
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Date: Mon, 29 Jan 2018 15:01:31 +0800
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Subject: [PATCH] clk: mvebu: a3700: fix the XTAL MODE pin to SB MPP9
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There is an error in the current code that the XTAL MODE
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pin was set to SB MPP31 which should be SB MPP9
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The latch register of SB MPP9 has different offset of 0x8
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Change-Id: I73d41d0c053808fd18944ed1d191aea817b6d21a
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Signed-off-by: Terry Zhou <bjzhou@marvell.com>
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---
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drivers/clk/mvebu/armada-37xx-xtal.c | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/drivers/clk/mvebu/armada-37xx-xtal.c b/drivers/clk/mvebu/armada-37xx-xtal.c
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index 612d65ede10a..5370514959e1 100644
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--- a/drivers/clk/mvebu/armada-37xx-xtal.c
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+++ b/drivers/clk/mvebu/armada-37xx-xtal.c
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@@ -15,8 +15,8 @@
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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-#define NB_GPIO1_LATCH 0xC
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-#define XTAL_MODE BIT(31)
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+#define NB_GPIO1_LATCH 0x8
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+#define XTAL_MODE BIT(9)
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static int armada_3700_xtal_clock_probe(struct platform_device *pdev)
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{
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