mirror of
https://github.com/Fishwaldo/build.git
synced 2025-03-25 16:21:32 +00:00
165 lines
5.2 KiB
Diff
165 lines
5.2 KiB
Diff
From 8fe651551acad197e8c776612b2fc16664d91f17 Mon Sep 17 00:00:00 2001
|
|
From: Neil Armstrong <narmstrong@baylibre.com>
|
|
Date: Fri, 13 Oct 2017 14:47:23 +0200
|
|
Subject: [PATCH 32/36] ARM64: dts: meson-gx: add VPU power domain
|
|
|
|
This patch adds support for the VPU Power Domain nodes, and attaches the
|
|
VPU power domain to the VPU node.
|
|
|
|
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
|
|
---
|
|
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 11 ++++++++
|
|
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 43 +++++++++++++++++++++++++++++
|
|
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 43 +++++++++++++++++++++++++++++
|
|
3 files changed, 97 insertions(+)
|
|
|
|
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
|
|
index ff27ce0..ace0e4b 100644
|
|
--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
|
|
+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
|
|
@@ -393,6 +393,12 @@
|
|
compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd";
|
|
reg = <0x0 0x0 0x0 0x100>;
|
|
|
|
+ pwrc_vpu: power-controller-vpu {
|
|
+ compatible = "amlogic,meson-gx-pwrc-vpu";
|
|
+ #power-domain-cells = <0>;
|
|
+ amlogic,hhi-sysctrl = <&sysctrl>;
|
|
+ };
|
|
+
|
|
clkc_AO: clock-controller {
|
|
compatible = "amlogic,meson-gx-aoclkc";
|
|
#clock-cells = <1>;
|
|
@@ -470,6 +476,11 @@
|
|
#size-cells = <2>;
|
|
ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
|
|
|
|
+ sysctrl: system-controller@0 {
|
|
+ compatible = "amlogic,meson-gx-hhi-sysctrl", "syscon", "simple-mfd";
|
|
+ reg = <0 0 0 0x400>;
|
|
+ };
|
|
+
|
|
mailbox: mailbox@404 {
|
|
compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
|
|
reg = <0 0x404 0 0x4c>;
|
|
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
|
|
index ef12d67..b5b6b33 100644
|
|
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
|
|
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
|
|
@@ -692,6 +692,48 @@
|
|
};
|
|
};
|
|
|
|
+&pwrc_vpu {
|
|
+ resets = <&reset RESET_VIU>,
|
|
+ <&reset RESET_VENC>,
|
|
+ <&reset RESET_VCBUS>,
|
|
+ <&reset RESET_BT656>,
|
|
+ <&reset RESET_DVIN_RESET>,
|
|
+ <&reset RESET_RDMA>,
|
|
+ <&reset RESET_VENCI>,
|
|
+ <&reset RESET_VENCP>,
|
|
+ <&reset RESET_VDAC>,
|
|
+ <&reset RESET_VDI6>,
|
|
+ <&reset RESET_VENCL>,
|
|
+ <&reset RESET_VID_LOCK>;
|
|
+ clocks = <&clkc CLKID_VPU>,
|
|
+ <&clkc CLKID_VAPB>;
|
|
+ clock-names = "vpu", "vapb";
|
|
+ /*
|
|
+ * VPU clocking is provided by two identical clock paths
|
|
+ * VPU_0 and VPU_1 muxed to a single clock by a glitch
|
|
+ * free mux to safely change frequency while running.
|
|
+ * Same for VAPB but with a final gate after the glitch free mux.
|
|
+ */
|
|
+ assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
|
|
+ <&clkc CLKID_VPU_0>,
|
|
+ <&clkc CLKID_VPU>, /* Glitch free mux */
|
|
+ <&clkc CLKID_VAPB_0_SEL>,
|
|
+ <&clkc CLKID_VAPB_0>,
|
|
+ <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
|
|
+ assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
|
|
+ <0>, /* Do Nothing */
|
|
+ <&clkc CLKID_VPU_0>,
|
|
+ <&clkc CLKID_FCLK_DIV4>,
|
|
+ <0>, /* Do Nothing */
|
|
+ <&clkc CLKID_VAPB_0>;
|
|
+ assigned-clock-rates = <0>, /* Do Nothing */
|
|
+ <666666666>,
|
|
+ <0>, /* Do Nothing */
|
|
+ <0>, /* Do Nothing */
|
|
+ <250000000>,
|
|
+ <0>; /* Do Nothing */
|
|
+};
|
|
+
|
|
&saradc {
|
|
compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
|
|
clocks = <&xtal>,
|
|
@@ -761,4 +803,5 @@
|
|
|
|
&vpu {
|
|
compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
|
|
+ power-domains = <&pwrc_vpu>;
|
|
};
|
|
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
|
|
index 02b52b6..d5c8952 100644
|
|
--- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
|
|
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
|
|
@@ -721,6 +721,48 @@
|
|
clock-names = "fast", "iface", "bclks", "mclk";
|
|
};
|
|
|
|
+&pwrc_vpu {
|
|
+ resets = <&reset RESET_VIU>,
|
|
+ <&reset RESET_VENC>,
|
|
+ <&reset RESET_VCBUS>,
|
|
+ <&reset RESET_BT656>,
|
|
+ <&reset RESET_DVIN_RESET>,
|
|
+ <&reset RESET_RDMA>,
|
|
+ <&reset RESET_VENCI>,
|
|
+ <&reset RESET_VENCP>,
|
|
+ <&reset RESET_VDAC>,
|
|
+ <&reset RESET_VDI6>,
|
|
+ <&reset RESET_VENCL>,
|
|
+ <&reset RESET_VID_LOCK>;
|
|
+ clocks = <&clkc CLKID_VPU>,
|
|
+ <&clkc CLKID_VAPB>;
|
|
+ clock-names = "vpu", "vapb";
|
|
+ /*
|
|
+ * VPU clocking is provided by two identical clock paths
|
|
+ * VPU_0 and VPU_1 muxed to a single clock by a glitch
|
|
+ * free mux to safely change frequency while running.
|
|
+ * Same for VAPB but with a final gate after the glitch free mux.
|
|
+ */
|
|
+ assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
|
|
+ <&clkc CLKID_VPU_0>,
|
|
+ <&clkc CLKID_VPU>, /* Glitch free mux */
|
|
+ <&clkc CLKID_VAPB_0_SEL>,
|
|
+ <&clkc CLKID_VAPB_0>,
|
|
+ <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
|
|
+ assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
|
|
+ <0>, /* Do Nothing */
|
|
+ <&clkc CLKID_VPU_0>,
|
|
+ <&clkc CLKID_FCLK_DIV4>,
|
|
+ <0>, /* Do Nothing */
|
|
+ <&clkc CLKID_VAPB_0>;
|
|
+ assigned-clock-rates = <0>, /* Do Nothing */
|
|
+ <666666666>,
|
|
+ <0>, /* Do Nothing */
|
|
+ <0>, /* Do Nothing */
|
|
+ <250000000>,
|
|
+ <0>; /* Do Nothing */
|
|
+};
|
|
+
|
|
&saradc {
|
|
compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
|
|
clocks = <&xtal>,
|
|
@@ -790,4 +832,5 @@
|
|
|
|
&vpu {
|
|
compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
|
|
+ power-domains = <&pwrc_vpu>;
|
|
};
|
|
--
|
|
2.7.4
|
|
|