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56 lines
1.3 KiB
Diff
56 lines
1.3 KiB
Diff
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
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index b36f9f42..02bbe834 100644
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--- a/arch/arm/boot/dts/sun8i-h3.dtsi
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+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
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@@ -47,28 +47,36 @@
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#address-cells = <1>;
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#size-cells = <0>;
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- cpu@0 {
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+ cpu0: cpu@0 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0>;
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+ clocks = <&ccu CLK_CPUX>;
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+ clock-names = "cpu";
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+ operating-points-v2 = <&cpu_opp_table>;
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+ cpu-supply = <®_cpu_fallback>;
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+ #cooling-cells = <2>;
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};
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cpu@1 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <1>;
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+ operating-points-v2 = <&cpu_opp_table>;
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};
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cpu@2 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <2>;
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+ operating-points-v2 = <&cpu_opp_table>;
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};
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cpu@3 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <3>;
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+ operating-points-v2 = <&cpu_opp_table>;
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};
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};
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@@ -79,6 +87,13 @@
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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+
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+ reg_cpu_fallback: reg_cpu_fallback {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vdd-cpux-dummy";
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+ regulator-min-microvolt = <1200000>;
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+ regulator-max-microvolt = <1200000>;
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+ };
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};
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&ccu {
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