mirror of
https://github.com/Fishwaldo/build.git
synced 2025-03-26 00:31:47 +00:00
79 lines
2.6 KiB
Diff
79 lines
2.6 KiB
Diff
From f04b205ac143413831b193f39fd9592665111d4b Mon Sep 17 00:00:00 2001
|
|
From: Lucas Stach <l.stach@pengutronix.de>
|
|
Date: Thu, 2 Apr 2015 17:29:04 +0200
|
|
Subject: [PATCH] drm/etnaviv: add devicetree bindings
|
|
|
|
Etnaviv follows the same priciple as imx-drm to have a virtual
|
|
master device node to bind all the individual GPU cores together
|
|
into one DRM device.
|
|
|
|
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
|
|
Acked-by: Rob Herring <robh@kernel.org>
|
|
---
|
|
.../bindings/display/etnaviv/etnaviv-drm.txt | 54 ++++++++++++++++++++++
|
|
1 file changed, 54 insertions(+)
|
|
create mode 100644 Documentation/devicetree/bindings/display/etnaviv/etnaviv-drm.txt
|
|
|
|
diff --git a/Documentation/devicetree/bindings/display/etnaviv/etnaviv-drm.txt b/Documentation/devicetree/bindings/display/etnaviv/etnaviv-drm.txt
|
|
new file mode 100644
|
|
index 0000000..ed5e0a7
|
|
--- /dev/null
|
|
+++ b/Documentation/devicetree/bindings/display/etnaviv/etnaviv-drm.txt
|
|
@@ -0,0 +1,54 @@
|
|
+Etnaviv DRM master device
|
|
+=========================
|
|
+
|
|
+The Etnaviv DRM master device is a virtual device needed to list all
|
|
+Vivante GPU cores that comprise the GPU subsystem.
|
|
+
|
|
+Required properties:
|
|
+- compatible: Should be one of
|
|
+ "fsl,imx-gpu-subsystem"
|
|
+ "marvell,dove-gpu-subsystem"
|
|
+- cores: Should contain a list of phandles pointing to Vivante GPU devices
|
|
+
|
|
+example:
|
|
+
|
|
+gpu-subsystem {
|
|
+ compatible = "fsl,imx-gpu-subsystem";
|
|
+ cores = <&gpu_2d>, <&gpu_3d>;
|
|
+};
|
|
+
|
|
+
|
|
+Vivante GPU core devices
|
|
+========================
|
|
+
|
|
+Required properties:
|
|
+- compatible: Should be "vivante,gc"
|
|
+ A more specific compatible is not needed, as the cores contain chip
|
|
+ identification registers at fixed locations, which provide all the
|
|
+ necessary information to the driver.
|
|
+- reg: should be register base and length as documented in the
|
|
+ datasheet
|
|
+- interrupts: Should contain the cores interrupt line
|
|
+- clocks: should contain one clock for entry in clock-names
|
|
+ see Documentation/devicetree/bindings/clock/clock-bindings.txt
|
|
+- clock-names:
|
|
+ - "bus": AXI/register clock
|
|
+ - "core": GPU core clock
|
|
+ - "shader": Shader clock (only required if GPU has feature PIPE_3D)
|
|
+
|
|
+Optional properties:
|
|
+- power-domains: a power domain consumer specifier according to
|
|
+ Documentation/devicetree/bindings/power/power_domain.txt
|
|
+
|
|
+example:
|
|
+
|
|
+gpu_3d: gpu@00130000 {
|
|
+ compatible = "vivante,gc";
|
|
+ reg = <0x00130000 0x4000>;
|
|
+ interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
|
|
+ <&clks IMX6QDL_CLK_GPU3D_CORE>,
|
|
+ <&clks IMX6QDL_CLK_GPU3D_SHADER>;
|
|
+ clock-names = "bus", "core", "shader";
|
|
+ power-domains = <&gpc 1>;
|
|
+};
|
|
--
|
|
2.7.0.rc3
|
|
|