build/patch/kernel/odroidc2-next/0071-clk-gxbb-add-cts_amclk.patch

From a47430e7903c2c9f68568b5f33ea4d508718df28 Mon Sep 17 00:00:00 2001
From: Jerome Brunet <jbrunet@baylibre.com>
Date: Tue, 24 Jan 2017 18:35:23 +0100
Subject: [PATCH 71/93] clk: gxbb: add cts_amclk

Add the i2s master clock also referred as cts_amclk

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

Conflicts:
	drivers/clk/meson/gxbb.c
	drivers/clk/meson/gxbb.h
---
 drivers/clk/meson/gxbb.c | 53 ++++++++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/meson/gxbb.h |  5 ++++-
 2 files changed, 57 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 4379a62..9e2e407 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -699,6 +699,51 @@
 	},
 };
 
+static struct clk_mux gxbb_cts_amclk_sel = {
+	.reg = (void *) HHI_AUD_CLK_CNTL,
+	.mask = 0x3,
+	.shift = 9,
+	/* Default parent unknown (register reset value: 0) */
+	.table = (u32[]){ 1, 2, 3 },
+	.lock = &clk_lock,
+		.hw.init = &(struct clk_init_data){
+		.name = "cts_amclk_sel",
+		.ops = &clk_mux_ops,
+		.parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" },
+		.num_parents = 2,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct meson_clk_audio_divider gxbb_cts_amclk_div = {
+	.div = {
+		.reg_off = HHI_AUD_CLK_CNTL,
+		.shift   = 0,
+		.width   = 8,
+	},
+	.lock = &clk_lock,
+	.hw.init = &(struct clk_init_data){
+		.name = "cts_amclk_div",
+		.ops = &meson_clk_audio_divider_ops,
+		.parent_names = (const char *[]){ "cts_amclk_sel" },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,
+	},
+};
+
+static struct clk_gate gxbb_cts_amclk = {
+	.reg = (void *) HHI_AUD_CLK_CNTL,
+	.bit_idx = 8,
+	.lock = &clk_lock,
+	.hw.init = &(struct clk_init_data){
+		.name = "cts_amclk",
+		.ops = &clk_gate_ops,
+		.parent_names = (const char *[]){ "cts_amclk_div" },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
 /* Everything Else (EE) domain gates */
 static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
 static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
@@ -890,6 +935,9 @@
 		[CLKID_SD_EMMC_B]	    = &gxbb_emmc_b.hw,
 		[CLKID_SD_EMMC_C]	    = &gxbb_emmc_c.hw,
 		[CLKID_MPLL0_PLL]	    = &gxbb_mpll0_pll.hw,
+		[CLKID_CTS_AMCLK]	    = &gxbb_cts_amclk.hw,
+		[CLKID_CTS_AMCLK_SEL]	    = &gxbb_cts_amclk_sel.hw,
+		[CLKID_CTS_AMCLK_DIV]	    = &gxbb_cts_amclk_div.hw,
 		[CLKID_MALI]		    = &gxbb_mali.hw,
 		/* This sentinel entry makes sure the table is large enough */
 		[NR_CLKS]		    = NULL, /* Sentinel */
@@ -998,6 +1046,7 @@
 	&gxbb_mali_0_en,
 	&gxbb_mali_1_en,
 	&gxbb_mpll0,
+	&gxbb_cts_amclk,
 };
 
 static struct clk_mux *gxbb_clk_muxes[] = {
@@ -1007,6 +1056,7 @@
 	&gxbb_mali,
 	&gxbb_mpeg_clk_sel,
 	&gxbb_sar_adc_clk_sel,
+	&gxbb_cts_amclk_sel,
 };
 
 static struct clk_divider *gxbb_clk_dividers[] = {
@@ -1108,6 +1158,9 @@ static int gxbb_clkc_probe(struct platform_device *pdev)
 		gxbb_gp0_init_regs[i] = clk_base +
 			(u64)gxbb_gp0_init_regs[i];
 
+	/* Populate base address for the audio divider */
+	gxbb_cts_amclk_div.base = clk_base;
+
 	/*
 	 * register all clks
 	 */
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index 366b766..298bfa5 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -266,11 +266,14 @@
 /* CLKID_SD_EMMC_B */
 /* CLKID_SD_EMMC_C */
 #define CLKID_MPLL0_PLL		  97
+#define CLKID_CTS_AMCLK		  98
+#define CLKID_CTS_AMCLK_SEL	  99
+#define CLKID_CTS_AMCLK_DIV	  100
 /* CLKID_MALI_0	*/
 /* CLKID_MALI_1	*/
 /* CLKID_MALI	*/
 
-#define NR_CLKS			  101
+#define NR_CLKS			  104
 
 /* include the CLKIDs that have been made part of the stable DT binding */
 #include <dt-bindings/clock/gxbb-clkc.h>
-- 
1.9.1