mirror of
https://github.com/Fishwaldo/build.git
synced 2025-07-24 05:48:41 +00:00
AR-1 - Adding support category for distributions AR-4 - Remove Allwinner legacy AR-5 - Drop Udoo family and move Udoo board into newly created imx6 family AR-9 - Rename sunxi-next to sunxi-legacy AR-10 - Rename sunxi-dev to sunxi-current AR-11 - Adding Radxa Rockpi S support AR-13 - Rename rockchip64-default to rockchip64-legacy AR-14 - Add rockchip64-current as mainline source AR-15 - Drop Rockchip 4.19.y NEXT, current become 5.3.y AR-16 - Rename RK3399 default to legacy AR-17 - Rename Odroid XU4 next and default to legacy 4.14.y, add DEV 5.4.y AR-18 - Add Odroid N2 current mainline AR-19 - Move Odroid C1 to meson family AR-20 - Rename mvebu64-default to mvebu64-legacy AR-21 - Rename mvebu-default to mvebu-legacy AR-22 - Rename mvebu-next to mvebu-current AR-23 - Drop meson64 default and next, current becomes former DEV 5.3.y AR-24 - Drop cubox family and move Cubox/Hummingboard boards under imx6 AR-26 - Adjust motd AR-27 - Enabling distribution release status AR-28 - Added new GCC compilers AR-29 - Implementing Ubuntu Eoan AR-30 - Add desktop packages per board or family AR-31 - Remove (Ubuntu/Debian) distribution name from image filename AR-32 - Move arch configs from configuration.sh to separate arm64 and armhf config files AR-33 - Revision numbers for beta builds changed to day_in_the_year AR-34 - Patches support linked patches AR-35 - Break meson64 family into gxbb and gxl AR-36 - Add Nanopineo2 Black AR-38 - Upgrade option from old branches to new one via armbian-config AR-41 - Show full timezone info AR-43 - Merge Odroid N2 to meson64 AR-44 - Enable FORCE_BOOTSCRIPT_UPDATE for all builds
86 lines
2.6 KiB
Diff
86 lines
2.6 KiB
Diff
From a977683c5364eb855601b152e20bd7b45f157874 Mon Sep 17 00:00:00 2001
|
|
From: Jernej Skrabec <jernej.skrabec@siol.net>
|
|
Date: Thu, 9 Aug 2018 18:52:13 +0200
|
|
Subject: [PATCH 083/146] clk: sunxi-ng: Add maximum rate constraint to NM PLLs
|
|
|
|
On some NM PLLs, frequency can be set above PLL working range.
|
|
|
|
Add a constraint for maximum supported rate. This way, drivers can
|
|
specify which is maximum allowed rate for PLL.
|
|
|
|
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
|
|
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
|
|
---
|
|
drivers/clk/sunxi-ng/ccu_nm.c | 7 +++++++
|
|
drivers/clk/sunxi-ng/ccu_nm.h | 30 ++++++++++++++++++++++++++++++
|
|
2 files changed, 37 insertions(+)
|
|
|
|
diff --git a/drivers/clk/sunxi-ng/ccu_nm.c b/drivers/clk/sunxi-ng/ccu_nm.c
|
|
index 4e2073307f34..6fe3c14f7b2d 100644
|
|
--- a/drivers/clk/sunxi-ng/ccu_nm.c
|
|
+++ b/drivers/clk/sunxi-ng/ccu_nm.c
|
|
@@ -124,6 +124,13 @@ static long ccu_nm_round_rate(struct clk_hw *hw, unsigned long rate,
|
|
return rate;
|
|
}
|
|
|
|
+ if (nm->max_rate && rate > nm->max_rate) {
|
|
+ rate = nm->max_rate;
|
|
+ if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV)
|
|
+ rate /= nm->fixed_post_div;
|
|
+ return rate;
|
|
+ }
|
|
+
|
|
if (ccu_frac_helper_has_rate(&nm->common, &nm->frac, rate)) {
|
|
if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV)
|
|
rate /= nm->fixed_post_div;
|
|
diff --git a/drivers/clk/sunxi-ng/ccu_nm.h b/drivers/clk/sunxi-ng/ccu_nm.h
|
|
index 1d8b459c50b7..de232f2199a6 100644
|
|
--- a/drivers/clk/sunxi-ng/ccu_nm.h
|
|
+++ b/drivers/clk/sunxi-ng/ccu_nm.h
|
|
@@ -38,6 +38,7 @@ struct ccu_nm {
|
|
|
|
unsigned int fixed_post_div;
|
|
unsigned int min_rate;
|
|
+ unsigned int max_rate;
|
|
|
|
struct ccu_common common;
|
|
};
|
|
@@ -115,6 +116,35 @@ struct ccu_nm {
|
|
}, \
|
|
}
|
|
|
|
+#define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(_struct, _name, \
|
|
+ _parent, _reg, \
|
|
+ _min_rate, _max_rate, \
|
|
+ _nshift, _nwidth, \
|
|
+ _mshift, _mwidth, \
|
|
+ _frac_en, _frac_sel, \
|
|
+ _frac_rate_0, \
|
|
+ _frac_rate_1, \
|
|
+ _gate, _lock, _flags) \
|
|
+ struct ccu_nm _struct = { \
|
|
+ .enable = _gate, \
|
|
+ .lock = _lock, \
|
|
+ .n = _SUNXI_CCU_MULT(_nshift, _nwidth), \
|
|
+ .m = _SUNXI_CCU_DIV(_mshift, _mwidth), \
|
|
+ .frac = _SUNXI_CCU_FRAC(_frac_en, _frac_sel, \
|
|
+ _frac_rate_0, \
|
|
+ _frac_rate_1), \
|
|
+ .min_rate = _min_rate, \
|
|
+ .max_rate = _max_rate, \
|
|
+ .common = { \
|
|
+ .reg = _reg, \
|
|
+ .features = CCU_FEATURE_FRACTIONAL, \
|
|
+ .hw.init = CLK_HW_INIT(_name, \
|
|
+ _parent, \
|
|
+ &ccu_nm_ops, \
|
|
+ _flags), \
|
|
+ }, \
|
|
+ }
|
|
+
|
|
#define SUNXI_CCU_NM_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \
|
|
_nshift, _nwidth, \
|
|
_mshift, _mwidth, \
|
|
--
|
|
2.17.1
|
|
|