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64 lines
2.1 KiB
Diff
64 lines
2.1 KiB
Diff
From eca91d4d36d78c3176480742532b247fd3d72fe0 Mon Sep 17 00:00:00 2001
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From: Simon Shields <simon@lineageos.org>
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Date: Sat, 13 Jan 2018 14:17:26 +1100
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Subject: [PATCH 038/146] ARM: dts: add gpu node to exynos4
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v2 (Qiang Yu):
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add vender string to exynos4 mali gpu
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Based off a similar commit for the Samsung Mali driver by
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Tobias Jakobi <tjakobi@math.uni-bielefeld.de>
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Signed-off-by: Simon Shields <simon@lineageos.org>
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Signed-off-by: Qiang Yu <yuq825@gmail.com>
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---
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arch/arm/boot/dts/exynos4.dtsi | 33 +++++++++++++++++++++++++++++++++
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1 file changed, 33 insertions(+)
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diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
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index 6085e92ac2d7..362461657136 100644
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--- a/arch/arm/boot/dts/exynos4.dtsi
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+++ b/arch/arm/boot/dts/exynos4.dtsi
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@@ -730,6 +730,39 @@
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status = "disabled";
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};
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+ gpu: gpu@13000000 {
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+ compatible = "samsung,exynos4-mali", "arm,mali-400";
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+ reg = <0x13000000 0x30000>;
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+ power-domains = <&pd_g3d>;
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+
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+ /*
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+ * Propagate VPLL output clock to SCLK_G3D and
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+ * ensure that the DIV_G3D divider is 1.
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+ */
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+ assigned-clocks = <&clock CLK_MOUT_G3D1>, <&clock CLK_MOUT_G3D>,
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+ <&clock CLK_FOUT_VPLL>, <&clock CLK_SCLK_G3D>;
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+ assigned-clock-parents = <&clock CLK_SCLK_VPLL>,
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+ <&clock CLK_MOUT_G3D1>;
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+ assigned-clock-rates = <0>, <0>, <160000000>, <160000000>;
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+
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+ clocks = <&clock CLK_SCLK_G3D>, <&clock CLK_G3D>;
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+ clock-names = "bus", "core";
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+
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+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "ppmmu0", "ppmmu1", "ppmmu2", "ppmmu3",
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+ "gpmmu", "pp0", "pp1", "pp2", "pp3", "gp";
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+ status = "disabled";
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+ };
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+
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tmu: tmu@100c0000 {
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interrupt-parent = <&combiner>;
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reg = <0x100C0000 0x100>;
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--
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2.17.1
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