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150ac0c2af
AR-1 - Adding support category for distributions AR-4 - Remove Allwinner legacy AR-5 - Drop Udoo family and move Udoo board into newly created imx6 family AR-9 - Rename sunxi-next to sunxi-legacy AR-10 - Rename sunxi-dev to sunxi-current AR-11 - Adding Radxa Rockpi S support AR-13 - Rename rockchip64-default to rockchip64-legacy AR-14 - Add rockchip64-current as mainline source AR-15 - Drop Rockchip 4.19.y NEXT, current become 5.3.y AR-16 - Rename RK3399 default to legacy AR-17 - Rename Odroid XU4 next and default to legacy 4.14.y, add DEV 5.4.y AR-18 - Add Odroid N2 current mainline AR-19 - Move Odroid C1 to meson family AR-20 - Rename mvebu64-default to mvebu64-legacy AR-21 - Rename mvebu-default to mvebu-legacy AR-22 - Rename mvebu-next to mvebu-current AR-23 - Drop meson64 default and next, current becomes former DEV 5.3.y AR-24 - Drop cubox family and move Cubox/Hummingboard boards under imx6 AR-26 - Adjust motd AR-27 - Enabling distribution release status AR-28 - Added new GCC compilers AR-29 - Implementing Ubuntu Eoan AR-30 - Add desktop packages per board or family AR-31 - Remove (Ubuntu/Debian) distribution name from image filename AR-32 - Move arch configs from configuration.sh to separate arm64 and armhf config files AR-33 - Revision numbers for beta builds changed to day_in_the_year AR-34 - Patches support linked patches AR-35 - Break meson64 family into gxbb and gxl AR-36 - Add Nanopineo2 Black AR-38 - Upgrade option from old branches to new one via armbian-config AR-41 - Show full timezone info AR-43 - Merge Odroid N2 to meson64 AR-44 - Enable FORCE_BOOTSCRIPT_UPDATE for all builds
113 lines
3.9 KiB
Diff
113 lines
3.9 KiB
Diff
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This adds a sysfs 'clock_source' attribute which can be used to query
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and set the clock source of the RTC, either 'internal' or 'external'.
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Important note: Probing the pins of the 32kHz crystal with a scope will
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not reliably tell you whether the (usually) more accurate external is
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selected! On a 'Cubietech Cubietruck' board, the author saw a stable
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32768Hz signal on the crystal, even though the internal oscillator was
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selected and the clock wildly drifting.
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Using adjtimex might help to figure out which oscillator is selected:
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~# echo internal > /sys/devices/.../1c20d00.rtc/clock_source
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~# adjtimex -n -c=3
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--- current --- -- suggested --
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cmos time system-cmos error_ppm tick freq tick freq
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1469627826 31.224561
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1469627835 31.858098 63353.6 10000 0
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1469627844 32.490782 63268.4 10000 0 9367 2069425
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~# echo external > /sys/devices/.../1c20d00.rtc/clock_source
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~# adjtimex -n -c=3
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--- current --- -- suggested --
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cmos time system-cmos error_ppm tick freq tick freq
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1469627851 32.883407
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1469627861 32.883380 -2.7 10000 0
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1469627871 32.883352 -2.8 10000 0 10000 185937
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Signed-off-by: Onno Kortmann <on...@gmx.net>
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---
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drivers/rtc/rtc-sunxi.c | 54 +++++++++++++++++++++++++++++++++++++++++++++++++
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1 file changed, 54 insertions(+)
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diff --git a/drivers/rtc/rtc-sunxi.c b/drivers/rtc/rtc-sunxi.c
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index abada60..3fcf571 100644
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--- a/drivers/rtc/rtc-sunxi.c
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+++ b/drivers/rtc/rtc-sunxi.c
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@@ -36,6 +36,8 @@
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#define SUNXI_LOSC_CTRL 0x0000
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#define SUNXI_LOSC_CTRL_RTC_HMS_ACC BIT(8)
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#define SUNXI_LOSC_CTRL_RTC_YMD_ACC BIT(7)
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+#define SUNXI_LOSC_OSC32K_SRC_SEL BIT(0)
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+#define SUNXI_LOSC_KEY_VALUE 0x16aa0000
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#define SUNXI_RTC_YMD 0x0004
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@@ -432,6 +434,50 @@ static const struct of_device_id sunxi_rtc_dt_ids[] = {
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};
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MODULE_DEVICE_TABLE(of, sunxi_rtc_dt_ids);
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+/* As per page 126 of the A20 manual, the lowest bit in LOSC_CTRL_REG controls
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+ * the 32.768KHz clock source to use for the RTC. Using the clock_source sysfs
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+ * attribute, the clock can be selected between external (accurate 32kHz
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+ * crystal) and internal (seems to be an inaccurate RC oscillator) mode. It
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+ * appears that this bit is non-volatile and will be kept in the RTC when the
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+ * system is powered off.
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+ */
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+static ssize_t sunxi_rtc_show_clock_source(struct device *dev,
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+ struct device_attribute *attr,
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+ char *buf)
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+{
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+ struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
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+ u32 val = readl(chip->base + SUNXI_LOSC_CTRL);
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+ if (val & SUNXI_LOSC_OSC32K_SRC_SEL)
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+ return sprintf(buf, "internal [external]\n");
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+ else
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+ return sprintf(buf, "[internal] external\n");
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+}
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+
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+static ssize_t sunxi_rtc_store_clock_source(struct device *dev,
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+ struct device_attribute *attr,
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+ const char *buf, size_t count) {
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+ struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
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+ u32 val = readl(chip->base + SUNXI_LOSC_CTRL);
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+
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+ if (strncmp(buf, "external", 8) == 0)
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+ val|=SUNXI_LOSC_OSC32K_SRC_SEL;
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+ else if (strncmp(buf, "internal", 8) == 0)
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+ val&=~SUNXI_LOSC_OSC32K_SRC_SEL;
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+ else
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+ return -EINVAL;
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+
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+ /* Writing this bit requires setting the upper 16 bit to 0x16aa (key
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+ * value). */
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+ val |= SUNXI_LOSC_KEY_VALUE;
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+
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+ writel(val, chip->base + SUNXI_LOSC_CTRL);
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+ return count;
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+}
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+
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+static DEVICE_ATTR(clock_source, S_IRUGO | S_IWUSR,
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+ sunxi_rtc_show_clock_source,
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+ sunxi_rtc_store_clock_source);
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+
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static int sunxi_rtc_probe(struct platform_device *pdev)
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{
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struct sunxi_rtc_dev *chip;
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@@ -490,6 +536,13 @@ static int sunxi_rtc_probe(struct platform_device *pdev)
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dev_info(&pdev->dev, "RTC enabled\n");
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+ ret = device_create_file(&pdev->dev, &dev_attr_clock_source);
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+ if (ret) {
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+ dev_err(&pdev->dev, "Unable to create sysfs entry: %s\n",
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+ dev_attr_clock_source.attr.name);
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+ return ret;
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+ }
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+
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return 0;
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}
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--
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2.2.0.34.gb8f29bf
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