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203 lines
4.7 KiB
Diff
203 lines
4.7 KiB
Diff
From ef9ca67d03cd6b18c03f69cd0141d63a672bc330 Mon Sep 17 00:00:00 2001
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From: Icenowy Zheng <icenowy@aosc.io>
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Date: Tue, 1 Aug 2017 21:12:58 +0800
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Subject: [PATCH] ARM: sun8i: h3: add display engine pipeline barebone
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As we have already the support for the DE2 on Allwinner H3, add the
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display engine pipeline device tree nodes to its DTSI file.
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The H5 pipeline has some differences and will be enabled later.
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Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
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---
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arch/arm/boot/dts/sun8i-h3.dtsi | 170 ++++++++++++++++++++++++++++++++++++++++
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1 file changed, 170 insertions(+)
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diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
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index b36f9f423c39d..75ad7b65a7fcd 100644
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--- a/arch/arm/boot/dts/sun8i-h3.dtsi
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+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
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@@ -41,6 +41,8 @@
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*/
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#include "sunxi-h3-h5.dtsi"
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+#include <dt-bindings/clock/sun8i-de2.h>
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+#include <dt-bindings/reset/sun8i-de2.h>
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/ {
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cpus {
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@@ -72,6 +74,174 @@
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};
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};
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+ de: display-engine {
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+ compatible = "allwinner,sun8i-h3-display-engine";
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+ allwinner,pipelines = <&mixer0>,
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+ <&mixer1>;
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+ status = "disabled";
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+ };
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+
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+ soc {
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+ display_clocks: clock@1000000 {
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+ compatible = "allwinner,sun8i-a83t-de2-clk";
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+ reg = <0x01000000 0x100000>;
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+ clocks = <&ccu CLK_BUS_DE>,
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+ <&ccu CLK_DE>;
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+ clock-names = "bus",
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+ "mod";
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+ resets = <&ccu RST_BUS_DE>;
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+ #clock-cells = <1>;
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+ #reset-cells = <1>;
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+ assigned-clocks = <&ccu CLK_DE>;
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+ assigned-clock-parents = <&ccu CLK_PLL_DE>;
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+ assigned-clock-rates = <432000000>;
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+ };
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+
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+ mixer0: mixer@1100000 {
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+ compatible = "allwinner,sun8i-h3-de2-mixer0";
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+ reg = <0x01100000 0x100000>;
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+ clocks = <&display_clocks CLK_BUS_MIXER0>,
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+ <&display_clocks CLK_MIXER0>;
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+ clock-names = "bus",
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+ "mod";
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+ resets = <&display_clocks RST_MIXER0>;
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+ status = "disabled";
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ mixer0_out: port@1 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <1>;
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+
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+ mixer0_out_tcon0: endpoint@0 {
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+ reg = <0>;
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+ remote-endpoint = <&tcon0_in_mixer0>;
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+ };
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+
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+ mixer0_out_tcon1: endpoint@1 {
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+ reg = <1>;
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+ remote-endpoint = <&tcon1_in_mixer0>;
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+ };
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+ };
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+ };
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+ };
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+
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+ mixer1: mixer@1200000 {
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+ compatible = "allwinner,sun8i-h3-de2-mixer1";
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+ reg = <0x01200000 0x100000>;
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+ clocks = <&display_clocks CLK_BUS_MIXER1>,
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+ <&display_clocks CLK_MIXER1>;
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+ clock-names = "bus",
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+ "mod";
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+ resets = <&display_clocks RST_WB>;
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+ status = "disabled";
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ mixer1_out: port@1 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <1>;
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+
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+ mixer1_out_tcon0: endpoint@0 {
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+ reg = <0>;
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+ remote-endpoint = <&tcon0_in_mixer1>;
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+ };
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+
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+ mixer1_out_tcon1: endpoint@1 {
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+ reg = <1>;
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+ remote-endpoint = <&tcon1_in_mixer1>;
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+ };
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+ };
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+ };
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+ };
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+
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+ tcon0: lcd-controller@1c0c000 {
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+ compatible = "allwinner,sun8i-h3-tcon";
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+ reg = <0x01c0c000 0x1000>;
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+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_TCON0>,
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+ <&ccu CLK_TCON0>;
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+ clock-names = "ahb",
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+ "tcon-ch1";
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+ resets = <&ccu RST_BUS_TCON0>;
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+ reset-names = "lcd";
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+ status = "disabled";
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ tcon0_in: port@0 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0>;
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+
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+ tcon0_in_mixer0: endpoint@0 {
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+ reg = <0>;
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+ remote-endpoint = <&mixer0_out_tcon0>;
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+ };
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+
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+ tcon0_in_mixer1: endpoint@1 {
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+ reg = <1>;
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+ remote-endpoint = <&mixer1_out_tcon0>;
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+ };
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+ };
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+
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+ tcon0_out: port@1 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <1>;
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+ };
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+ };
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+ };
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+
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+ tcon1: lcd-controller@1c0d000 {
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+ compatible = "allwinner,sun8i-h3-tcon";
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+ reg = <0x01c0d000 0x1000>;
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+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_TCON1>,
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+ <&ccu CLK_TVE>;
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+ clock-names = "ahb",
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+ "tcon-ch1";
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+ resets = <&ccu RST_BUS_TCON1>;
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+ reset-names = "lcd";
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+ status = "disabled";
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ tcon1_in: port@0 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0>;
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+
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+ tcon1_in_mixer0: endpoint@0 {
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+ reg = <0>;
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+ remote-endpoint = <&mixer0_out_tcon1>;
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+ };
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+
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+ tcon1_in_mixer1: endpoint@1 {
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+ reg = <1>;
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+ remote-endpoint = <&mixer1_out_tcon1>;
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+ };
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+ };
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+
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+ tcon1_out: port@1 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <1>;
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+ };
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+ };
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+ };
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+ };
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+
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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