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98 lines
2.7 KiB
Text
98 lines
2.7 KiB
Text
diff --git a/board/solidrun/mx6_cubox-i/mx6_cubox-i.c b/board/solidrun/mx6_cubox-i/mx6_cubox-i.c
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index 7c49f4e..6c92c1d
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--- a/board/solidrun/mx6_cubox-i/mx6_cubox-i.c
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+++ b/board/solidrun/mx6_cubox-i/mx6_cubox-i.c
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@@ -78,9 +78,85 @@ DECLARE_GLOBAL_DATA_PTR;
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int hb_cuboxi_ = 0; /* 2 is HummingBoard2, 1 is HummingBoard, 0 is CuBox-i */
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+/*
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+ * Check memory range for valid RAM. A simple memory test determines
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+ * the actually available RAM size between addresses `base' and
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+ * `base + maxsize'.
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+ * This algorithm uses value MEM_STRIDE (like 128MByte) steps instead of the one bit right shift
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+ * algorithm originally used in get_ram_size() since a 4GByte memory setup in
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+ * a 32bit architecture forbids addressing all the memory, so right shift
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+ * algorithm that assumes total memory size is exponents of 2 would fail.
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+ */
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+#define MEM_STRIDE 0x04000000
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+static u32 get_ram_size_stride_test(u32 *base, u32 maxsize)
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+{
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+ volatile u32 *addr;
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+ u32 save[64];
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+ u32 cnt;
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+ long size;
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+ u32 size_tmp;
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+ int i = 0;
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+ cnt = maxsize;
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+ /* First save the data */
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+ for (cnt = 0; cnt < maxsize; cnt += MEM_STRIDE) {
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+ addr = (volatile u32 *)((u32)base + cnt); /* pointer arith! */
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+ sync ();
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+ save[i] = *addr;
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+ i++;
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+ sync ();
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+ }
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+ /* First write a signature */
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+ * (volatile u32 *) base = 0x12345678;
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+ for (size_tmp = MEM_STRIDE; size_tmp < (u32)maxsize; size_tmp += MEM_STRIDE) {
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+ long tmp;
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+ * (volatile u32 *)((u32)base + (u32)size_tmp) = (u32)size_tmp;
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+ sync ();
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+ tmp = * (volatile u32 *)((u32)base + (u32)size);
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+ if (tmp == size_tmp) { /* Looks we reached overlapping address */
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+ break;
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+ }
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+ }
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+ /* Resotre the data */
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+ for (cnt = (maxsize - MEM_STRIDE); i > 0; cnt -= MEM_STRIDE) {
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+ i--;
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+ addr = (volatile u32 *)((u32)base + cnt); /* pointer arith! */
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+ sync ();
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+ * addr = save[i];
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+ sync ();
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+ }
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+ maxsize = size_tmp;
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+
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+ return (maxsize);
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+}
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+
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int dram_init(void)
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{
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- gd->ram_size = imx_ddr_size();
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+ uint cpurev, imxtype;
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+ u32 sdram_size;
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+
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+ cpurev = get_cpu_rev();
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+ imxtype = (cpurev & 0xFF000) >> 12;
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+
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+ switch (imxtype){
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+ case MXC_CPU_MX6SOLO:
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+ sdram_size = 0x20000000;
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+ break;
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+ case MXC_CPU_MX6Q:
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+ {
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+ /* Read first the snoop control unit config register */
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+ u32 scu_config = *(u32 *)(SCU_BASE_ADDR + 0x4);
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+ if ((scu_config & 0x3) == 0x3) /* Quad core */
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+ sdram_size = 0xf0000000;
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+ else /* Dual core */
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+ sdram_size = 0x40000000;
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+ break;
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+ }
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+ case MXC_CPU_MX6DL:
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+ default:
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+ sdram_size = 0x40000000;
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+ break;
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+ }
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+ gd->ram_size = get_ram_size_stride_test((void *)PHYS_SDRAM, sdram_size);
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return 0;
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}
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@@ -624,4 +700,4 @@ int board_late_init(void)
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#endif
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return 0;
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-}
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+}
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\ No newline at end of file
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