mirror of
https://github.com/Fishwaldo/build.git
synced 2025-07-22 21:08:49 +00:00
41b589372f
Some clenaup, removed dragonboard820c, adjusted board descriptions, added another OPP for 3288 family,
184 lines
3.7 KiB
Diff
184 lines
3.7 KiB
Diff
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4-common.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4-common.dtsi
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index 7cff5d61..d2e1334b 100644
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--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4-common.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4-common.dtsi
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@@ -67,24 +67,6 @@
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model = "NanoPi 4 Series";
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};
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- fiq_debugger: fiq-debugger {
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- compatible = "rockchip,fiq-debugger";
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- rockchip,serial-id = <2>;
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- rockchip,signal-irq = <182>;
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- rockchip,wake-irq = <0>;
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- rockchip,irq-mode-enable = <1>; /* If enable uart uses irq instead of fiq */
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- rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */
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- pinctrl-names = "default";
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- pinctrl-0 = <&uart2c_xfer>;
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- };
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-
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- xin32k: xin32k {
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- compatible = "fixed-clock";
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- clock-frequency = <32768>;
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- clock-output-names = "xin32k";
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- #clock-cells = <0>;
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- };
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-
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clkin_gmac: external-gmac-clock {
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compatible = "fixed-clock";
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clock-frequency = <125000000>;
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@@ -475,14 +457,8 @@
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status = "okay";
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};
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-&uart4 {
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- status = "okay";
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-};
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-
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&vopb {
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status = "okay";
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- assigned-clocks = <&cru DCLK_VOP0_DIV>;
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- assigned-clock-parents = <&cru PLL_VPLL>;
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};
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&vopb_mmu {
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@@ -491,8 +467,6 @@
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&vopl {
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status = "okay";
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- assigned-clocks = <&cru DCLK_VOP1_DIV>;
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- assigned-clock-parents = <&cru PLL_CPLL>;
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};
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&vopl_mmu {
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@@ -511,18 +485,13 @@
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//allocator = <0>;
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};
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-&rga {
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- status = "okay";
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-};
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-
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&display_subsystem {
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status = "okay";
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};
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&edp {
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- status = "okay";
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+ status = "disabled";
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force-hpd;
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- /delete-property/ pinctrl-0;
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ports {
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port@1 {
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@@ -535,45 +504,28 @@
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};
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};
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-&edp_in_vopb {
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+&edp_in_vopl {
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status = "disabled";
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};
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&route_edp {
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status = "okay";
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- logo,mode = "center";
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- connect = <&vopl_out_edp>;
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};
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&cdn_dp {
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- status = "okay";
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+ status = "disabled";
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extcon = <&fusb0>;
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phys = <&tcphy0_dp>;
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};
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-&dp_in_vopl {
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- status = "disabled";
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-};
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-
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-&hdmi_in_vopl {
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- status = "disabled";
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-};
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-
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&hdmi {
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- /* remove the hdmi_i2c_xfer */
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- pinctrl-0 = <&hdmi_cec>;
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+ /* remove the hdmi_cec, reused by edp_hpd */
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+ pinctrl-0 = <&hdmi_i2c_xfer>;
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#address-cells = <1>;
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#size-cells = <0>;
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#sound-dai-cells = <0>;
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status = "okay";
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ddc-i2c-bus = <&i2c7>;
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- rockchip,defaultmode = <16>; /* CEA 1920x1080@60Hz */
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-};
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-
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-&route_hdmi {
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- status = "disabled";
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- logo,mode = "center";
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- connect = <&vopb_out_hdmi>;
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};
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&cif_isp0 {
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@@ -848,13 +800,11 @@
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compatible = "omnivision,ov13850-v4l2-i2c-subdev";
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reg = <0x10>;
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device_type = "v4l2-i2c-subdev";
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-
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clocks = <&cru SCLK_CIF_OUT>;
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clock-names = "clk_cif_out";
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pinctrl-names = "rockchip,camera_default", "rockchip,camera_sleep";
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pinctrl-0 = <&cam0_default_pins>;
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pinctrl-1 = <&cam0_sleep_pins>;
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-
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rockchip,pd-gpio = <&gpio2 28 GPIO_ACTIVE_LOW>;
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rockchip,rst-gpio = <&gpio2 27 GPIO_ACTIVE_LOW>;
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@@ -939,11 +889,6 @@
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#sound-dai-cells = <0>;
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};
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-&i2s1 {
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- assigned-clocks = <&cru SCLK_I2S_8CH>;
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- assigned-clock-parents = <&cru SCLK_I2S1_8CH>;
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-};
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-
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&i2s2 {
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#sound-dai-cells = <0>;
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status = "okay";
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@@ -968,9 +913,16 @@
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};
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&pcie0 {
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- status = "okay";
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- ep-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>;
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- num-lanes = <4>;
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+ assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
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+ assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
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+ assigned-clock-rates = <100000000>;
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+ status = "okay";
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+ ep-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>;
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+ num-lanes = <4>;
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+ vpcie3v3-supply = <&vcc3v3_sys>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pcie_clkreqn_cpm>;
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+ max-link-speed = <2>;
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};
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&pwm_bl {
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@@ -1154,14 +1106,6 @@
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};
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&pinctrl {
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- edp {
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- /delete-node/ edp-hpd;
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- };
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-
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- hdmi {
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- /delete-node/ hdmi-i2c-xfer;
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- };
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-
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pmic {
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pmic_int_l: pmic-int-l {
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rockchip,pins = <1 21 RK_FUNC_GPIO &pcfg_pull_up>;
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