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https://github.com/Fishwaldo/build.git
synced 2025-07-23 21:39:02 +00:00
8f9f12065e
* Moved rockchip-dev to kernel 5.7, removed already upstreamed patch (1016), adjusted conflicting patch (1015) Most kernel configuration answer left at default, notables: - Wireguard (as module) - Zswap default compression set to LZO - RK3288 GPIOMEM (as module) - Enabled some new DMABUF bits (heaps, cmas) - Hantro driver - F2FS compression * Disabled rx/tx dma for uarts, on my board causes system freeze during bluetooth initialization. Don't know if they ever worked, tried to enable them ages ago and they were already not working
40 lines
1.3 KiB
Diff
40 lines
1.3 KiB
Diff
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
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index 0cd88774d..07681f1f0 100644
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--- a/arch/arm/boot/dts/rk3288.dtsi
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+++ b/arch/arm/boot/dts/rk3288.dtsi
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@@ -420,8 +420,6 @@
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reg-io-width = <4>;
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clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
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clock-names = "baudclk", "apb_pclk";
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- dmas = <&dmac_peri 1>, <&dmac_peri 2>;
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- dma-names = "tx", "rx";
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_xfer>;
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status = "disabled";
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@@ -435,8 +433,6 @@
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reg-io-width = <4>;
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clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
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clock-names = "baudclk", "apb_pclk";
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- dmas = <&dmac_peri 3>, <&dmac_peri 4>;
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- dma-names = "tx", "rx";
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_xfer>;
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status = "disabled";
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@@ -463,8 +459,6 @@
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reg-io-width = <4>;
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clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
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clock-names = "baudclk", "apb_pclk";
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- dmas = <&dmac_peri 7>, <&dmac_peri 8>;
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- dma-names = "tx", "rx";
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pinctrl-names = "default";
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pinctrl-0 = <&uart3_xfer>;
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status = "disabled";
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@@ -478,8 +472,6 @@
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reg-io-width = <4>;
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clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
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clock-names = "baudclk", "apb_pclk";
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- dmas = <&dmac_peri 9>, <&dmac_peri 10>;
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- dma-names = "tx", "rx";
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pinctrl-names = "default";
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pinctrl-0 = <&uart4_xfer>;
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status = "disabled";
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