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1447 lines
69 KiB
Text
1447 lines
69 KiB
Text
From f7ac5b5f4a875c93367962ddbe582efb09c4c370 Mon Sep 17 00:00:00 2001
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From: Joachim Damm <dammj@gmx.de>
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Date: Fri, 17 Jun 2016 18:34:41 +0200
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Subject: [PATCH] fix reconnect error H3 cec driver
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---
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drivers/video/sunxi/disp2/hdmi/aw/dw_hdmi.h | 1003 +++++++++++++------------
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drivers/video/sunxi/disp2/hdmi/aw/hdmi_cec.c | 126 +++-
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drivers/video/sunxi/disp2/hdmi/aw/hdmi_core.c | 8 +-
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drivers/video/sunxi/disp2/hdmi/aw/hdmi_edid.h | 42 +-
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drivers/video/sunxi/disp2/hdmi/drv_hdmi.c | 19 +
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drivers/video/sunxi/disp2/hdmi/drv_hdmi_i.h | 3 +
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6 files changed, 646 insertions(+), 555 deletions(-)
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mode change 100644 => 100755 drivers/video/sunxi/disp2/hdmi/aw/dw_hdmi.h
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diff --git a/drivers/video/sunxi/disp2/hdmi/aw/dw_hdmi.h b/drivers/video/sunxi/disp2/hdmi/aw/dw_hdmi.h
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index bdfae93..5e99e71
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--- a/drivers/video/sunxi/disp2/hdmi/aw/dw_hdmi.h
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+++ b/drivers/video/sunxi/disp2/hdmi/aw/dw_hdmi.h
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@@ -22,543 +22,543 @@
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#define __DW_HDMI_H__
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/*
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- * Hdmi controller registers
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+ * Hdmi controller registers for Allwinner H3
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*/
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/* Identification Registers */
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#define HDMI_DESIGN_ID 0x0000
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#define HDMI_REVISION_ID 0x0001
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-#define HDMI_PRODUCT_ID0 0x0002
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-#define HDMI_PRODUCT_ID1 0x0003
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-#define HDMI_CONFIG0_ID 0x0004
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-#define HDMI_CONFIG1_ID 0x0005
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-#define HDMI_CONFIG2_ID 0x0006
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-#define HDMI_CONFIG3_ID 0x0007
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+#define HDMI_PRODUCT_ID0 0x8000
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+#define HDMI_PRODUCT_ID1 0x8001
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+#define HDMI_CONFIG0_ID 0x0002
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+#define HDMI_CONFIG1_ID 0x0003
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+#define HDMI_CONFIG2_ID 0x8002
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+#define HDMI_CONFIG3_ID 0x8003
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/* Interrupt Registers */
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-#define HDMI_IH_FC_STAT0 0x0100
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-#define HDMI_IH_FC_STAT1 0x0101
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-#define HDMI_IH_FC_STAT2 0x0102
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-#define HDMI_IH_AS_STAT0 0x0103
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-#define HDMI_IH_PHY_STAT0 0x0104
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-#define HDMI_IH_I2CM_STAT0 0x0105
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-#define HDMI_IH_CEC_STAT0 0x0106
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-#define HDMI_IH_VP_STAT0 0x0107
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-#define HDMI_IH_I2CMPHY_STAT0 0x0108
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-#define HDMI_IH_AHBDMAAUD_STAT0 0x0109
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-
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-#define HDMI_IH_MUTE_FC_STAT0 0x0180
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-#define HDMI_IH_MUTE_FC_STAT1 0x0181
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-#define HDMI_IH_MUTE_FC_STAT2 0x0182
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-#define HDMI_IH_MUTE_AS_STAT0 0x0183
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-#define HDMI_IH_MUTE_PHY_STAT0 0x0184
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-#define HDMI_IH_MUTE_I2CM_STAT0 0x0185
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-#define HDMI_IH_MUTE_CEC_STAT0 0x0186
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-#define HDMI_IH_MUTE_VP_STAT0 0x0187
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-#define HDMI_IH_MUTE_I2CMPHY_STAT0 0x0188
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-#define HDMI_IH_MUTE_AHBDMAAUD_STAT0 0x0189
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-#define HDMI_IH_MUTE 0x01FF
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+#define HDMI_IH_FC_STAT0 0x0010
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+#define HDMI_IH_FC_STAT1 0x0011
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+#define HDMI_IH_FC_STAT2 0x8010
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+#define HDMI_IH_AS_STAT0 0x8011
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+#define HDMI_IH_PHY_STAT0 0x0012
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+#define HDMI_IH_I2CM_STAT0 0x0013
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+#define HDMI_IH_CEC_STAT0 0x8012
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+#define HDMI_IH_VP_STAT0 0x8013
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+#define HDMI_IH_I2CMPHY_STAT0 0x4010
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+#define HDMI_IH_AHBDMAAUD_STAT0 0x4011
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+
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+#define HDMI_IH_MUTE_FC_STAT0 0x1010
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+#define HDMI_IH_MUTE_FC_STAT1 0x1011
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+#define HDMI_IH_MUTE_FC_STAT2 0x9010
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+#define HDMI_IH_MUTE_AS_STAT0 0x9011
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+#define HDMI_IH_MUTE_PHY_STAT0 0x1012
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+#define HDMI_IH_MUTE_I2CM_STAT0 0x1013
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+#define HDMI_IH_MUTE_CEC_STAT0 0x9012
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+#define HDMI_IH_MUTE_VP_STAT0 0x9013
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+#define HDMI_IH_MUTE_I2CMPHY_STAT0 0x5010
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+#define HDMI_IH_MUTE_AHBDMAAUD_STAT0 0x5011
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+#define HDMI_IH_MUTE 0xf01f
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/* Video Sample Registers */
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-#define HDMI_TX_INVID0 0x0200
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-#define HDMI_TX_INSTUFFING 0x0201
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-#define HDMI_TX_GYDATA0 0x0202
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-#define HDMI_TX_GYDATA1 0x0203
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-#define HDMI_TX_RCRDATA0 0x0204
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-#define HDMI_TX_RCRDATA1 0x0205
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-#define HDMI_TX_BCBDATA0 0x0206
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-#define HDMI_TX_BCBDATA1 0x0207
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+#define HDMI_TX_INVID0 0x0800
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+#define HDMI_TX_INSTUFFING 0x0801
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+#define HDMI_TX_GYDATA0 0x8800
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+#define HDMI_TX_GYDATA1 0x8801
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+#define HDMI_TX_RCRDATA0 0x0802
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+#define HDMI_TX_RCRDATA1 0x0803
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+#define HDMI_TX_BCBDATA0 0x8802
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+#define HDMI_TX_BCBDATA1 0x8803
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/* Video Packetizer Registers */
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-#define HDMI_VP_STATUS 0x0800
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-#define HDMI_VP_PR_CD 0x0801
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-#define HDMI_VP_STUFF 0x0802
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-#define HDMI_VP_REMAP 0x0803
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-#define HDMI_VP_CONF 0x0804
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-#define HDMI_VP_STAT 0x0805
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-#define HDMI_VP_INT 0x0806
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-#define HDMI_VP_MASK 0x0807
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-#define HDMI_VP_POL 0x0808
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+#define HDMI_VP_STATUS 0x0400
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+#define HDMI_VP_PR_CD 0x0401
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+#define HDMI_VP_STUFF 0x8400
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+#define HDMI_VP_REMAP 0x8401
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+#define HDMI_VP_CONF 0x0402
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+#define HDMI_VP_STAT 0x0403
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+#define HDMI_VP_INT 0x8402
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+#define HDMI_VP_MASK 0x8403
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+#define HDMI_VP_POL 0x4400
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/* Frame Composer Registers */
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-#define HDMI_FC_INVIDCONF 0x1000
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-#define HDMI_FC_INHACTV0 0x1001
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-#define HDMI_FC_INHACTV1 0x1002
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-#define HDMI_FC_INHBLANK0 0x1003
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-#define HDMI_FC_INHBLANK1 0x1004
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-#define HDMI_FC_INVACTV0 0x1005
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-#define HDMI_FC_INVACTV1 0x1006
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-#define HDMI_FC_INVBLANK 0x1007
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-#define HDMI_FC_HSYNCINDELAY0 0x1008
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-#define HDMI_FC_HSYNCINDELAY1 0x1009
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-#define HDMI_FC_HSYNCINWIDTH0 0x100A
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-#define HDMI_FC_HSYNCINWIDTH1 0x100B
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-#define HDMI_FC_VSYNCINDELAY 0x100C
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-#define HDMI_FC_VSYNCINWIDTH 0x100D
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-#define HDMI_FC_INFREQ0 0x100E
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-#define HDMI_FC_INFREQ1 0x100F
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-#define HDMI_FC_INFREQ2 0x1010
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-#define HDMI_FC_CTRLDUR 0x1011
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-#define HDMI_FC_EXCTRLDUR 0x1012
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-#define HDMI_FC_EXCTRLSPAC 0x1013
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-#define HDMI_FC_CH0PREAM 0x1014
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-#define HDMI_FC_CH1PREAM 0x1015
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-#define HDMI_FC_CH2PREAM 0x1016
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-#define HDMI_FC_AVICONF3 0x1017
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-#define HDMI_FC_GCP 0x1018
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-#define HDMI_FC_AVICONF0 0x1019
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-#define HDMI_FC_AVICONF1 0x101A
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-#define HDMI_FC_AVICONF2 0x101B
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-#define HDMI_FC_AVIVID 0x101C
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-#define HDMI_FC_AVIETB0 0x101D
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-#define HDMI_FC_AVIETB1 0x101E
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-#define HDMI_FC_AVISBB0 0x101F
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-#define HDMI_FC_AVISBB1 0x1020
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-#define HDMI_FC_AVIELB0 0x1021
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-#define HDMI_FC_AVIELB1 0x1022
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-#define HDMI_FC_AVISRB0 0x1023
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-#define HDMI_FC_AVISRB1 0x1024
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-#define HDMI_FC_AUDICONF0 0x1025
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-#define HDMI_FC_AUDICONF1 0x1026
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-#define HDMI_FC_AUDICONF2 0x1027
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-#define HDMI_FC_AUDICONF3 0x1028
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-#define HDMI_FC_VSDIEEEID0 0x1029
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-#define HDMI_FC_VSDSIZE 0x102A
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-#define HDMI_FC_VSDIEEEID1 0x1030
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-#define HDMI_FC_VSDIEEEID2 0x1031
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-#define HDMI_FC_VSDPAYLOAD0 0x1032
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-#define HDMI_FC_VSDPAYLOAD1 0x1033
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-#define HDMI_FC_VSDPAYLOAD2 0x1034
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-#define HDMI_FC_VSDPAYLOAD3 0x1035
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-#define HDMI_FC_VSDPAYLOAD4 0x1036
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-#define HDMI_FC_VSDPAYLOAD5 0x1037
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-#define HDMI_FC_VSDPAYLOAD6 0x1038
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-#define HDMI_FC_VSDPAYLOAD7 0x1039
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-#define HDMI_FC_VSDPAYLOAD8 0x103A
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-#define HDMI_FC_VSDPAYLOAD9 0x103B
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-#define HDMI_FC_VSDPAYLOAD10 0x103C
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-#define HDMI_FC_VSDPAYLOAD11 0x103D
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-#define HDMI_FC_VSDPAYLOAD12 0x103E
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-#define HDMI_FC_VSDPAYLOAD13 0x103F
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-#define HDMI_FC_VSDPAYLOAD14 0x1040
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-#define HDMI_FC_VSDPAYLOAD15 0x1041
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-#define HDMI_FC_VSDPAYLOAD16 0x1042
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-#define HDMI_FC_VSDPAYLOAD17 0x1043
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-#define HDMI_FC_VSDPAYLOAD18 0x1044
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-#define HDMI_FC_VSDPAYLOAD19 0x1045
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-#define HDMI_FC_VSDPAYLOAD20 0x1046
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-#define HDMI_FC_VSDPAYLOAD21 0x1047
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-#define HDMI_FC_VSDPAYLOAD22 0x1048
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-#define HDMI_FC_VSDPAYLOAD23 0x1049
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-#define HDMI_FC_SPDVENDORNAME0 0x104A
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-#define HDMI_FC_SPDVENDORNAME1 0x104B
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-#define HDMI_FC_SPDVENDORNAME2 0x104C
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-#define HDMI_FC_SPDVENDORNAME3 0x104D
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-#define HDMI_FC_SPDVENDORNAME4 0x104E
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-#define HDMI_FC_SPDVENDORNAME5 0x104F
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-#define HDMI_FC_SPDVENDORNAME6 0x1050
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-#define HDMI_FC_SPDVENDORNAME7 0x1051
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-#define HDMI_FC_SDPPRODUCTNAME0 0x1052
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-#define HDMI_FC_SDPPRODUCTNAME1 0x1053
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-#define HDMI_FC_SDPPRODUCTNAME2 0x1054
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-#define HDMI_FC_SDPPRODUCTNAME3 0x1055
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-#define HDMI_FC_SDPPRODUCTNAME4 0x1056
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-#define HDMI_FC_SDPPRODUCTNAME5 0x1057
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-#define HDMI_FC_SDPPRODUCTNAME6 0x1058
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-#define HDMI_FC_SDPPRODUCTNAME7 0x1059
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-#define HDMI_FC_SDPPRODUCTNAME8 0x105A
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-#define HDMI_FC_SDPPRODUCTNAME9 0x105B
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-#define HDMI_FC_SDPPRODUCTNAME10 0x105C
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-#define HDMI_FC_SDPPRODUCTNAME11 0x105D
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-#define HDMI_FC_SDPPRODUCTNAME12 0x105E
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-#define HDMI_FC_SDPPRODUCTNAME13 0x105F
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-#define HDMI_FC_SDPPRODUCTNAME14 0x1060
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-#define HDMI_FC_SPDPRODUCTNAME15 0x1061
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-#define HDMI_FC_SPDDEVICEINF 0x1062
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-#define HDMI_FC_AUDSCONF 0x1063
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-#define HDMI_FC_AUDSSTAT 0x1064
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-#define HDMI_FC_DATACH0FILL 0x1070
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-#define HDMI_FC_DATACH1FILL 0x1071
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-#define HDMI_FC_DATACH2FILL 0x1072
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-#define HDMI_FC_CTRLQHIGH 0x1073
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-#define HDMI_FC_CTRLQLOW 0x1074
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-#define HDMI_FC_ACP0 0x1075
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-#define HDMI_FC_ACP28 0x1076
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-#define HDMI_FC_ACP27 0x1077
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-#define HDMI_FC_ACP26 0x1078
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-#define HDMI_FC_ACP25 0x1079
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-#define HDMI_FC_ACP24 0x107A
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-#define HDMI_FC_ACP23 0x107B
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-#define HDMI_FC_ACP22 0x107C
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-#define HDMI_FC_ACP21 0x107D
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-#define HDMI_FC_ACP20 0x107E
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-#define HDMI_FC_ACP19 0x107F
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-#define HDMI_FC_ACP18 0x1080
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-#define HDMI_FC_ACP17 0x1081
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-#define HDMI_FC_ACP16 0x1082
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-#define HDMI_FC_ACP15 0x1083
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-#define HDMI_FC_ACP14 0x1084
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-#define HDMI_FC_ACP13 0x1085
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-#define HDMI_FC_ACP12 0x1086
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-#define HDMI_FC_ACP11 0x1087
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-#define HDMI_FC_ACP10 0x1088
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-#define HDMI_FC_ACP9 0x1089
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-#define HDMI_FC_ACP8 0x108A
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-#define HDMI_FC_ACP7 0x108B
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-#define HDMI_FC_ACP6 0x108C
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-#define HDMI_FC_ACP5 0x108D
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-#define HDMI_FC_ACP4 0x108E
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-#define HDMI_FC_ACP3 0x108F
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-#define HDMI_FC_ACP2 0x1090
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-#define HDMI_FC_ACP1 0x1091
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-#define HDMI_FC_ISCR1_0 0x1092
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-#define HDMI_FC_ISCR1_16 0x1093
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-#define HDMI_FC_ISCR1_15 0x1094
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-#define HDMI_FC_ISCR1_14 0x1095
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-#define HDMI_FC_ISCR1_13 0x1096
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-#define HDMI_FC_ISCR1_12 0x1097
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-#define HDMI_FC_ISCR1_11 0x1098
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-#define HDMI_FC_ISCR1_10 0x1099
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-#define HDMI_FC_ISCR1_9 0x109A
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-#define HDMI_FC_ISCR1_8 0x109B
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-#define HDMI_FC_ISCR1_7 0x109C
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-#define HDMI_FC_ISCR1_6 0x109D
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-#define HDMI_FC_ISCR1_5 0x109E
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-#define HDMI_FC_ISCR1_4 0x109F
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-#define HDMI_FC_ISCR1_3 0x10A0
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-#define HDMI_FC_ISCR1_2 0x10A1
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-#define HDMI_FC_ISCR1_1 0x10A2
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-#define HDMI_FC_ISCR2_15 0x10A3
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-#define HDMI_FC_ISCR2_14 0x10A4
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-#define HDMI_FC_ISCR2_13 0x10A5
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-#define HDMI_FC_ISCR2_12 0x10A6
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-#define HDMI_FC_ISCR2_11 0x10A7
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-#define HDMI_FC_ISCR2_10 0x10A8
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-#define HDMI_FC_ISCR2_9 0x10A9
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-#define HDMI_FC_ISCR2_8 0x10AA
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-#define HDMI_FC_ISCR2_7 0x10AB
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-#define HDMI_FC_ISCR2_6 0x10AC
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-#define HDMI_FC_ISCR2_5 0x10AD
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-#define HDMI_FC_ISCR2_4 0x10AE
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-#define HDMI_FC_ISCR2_3 0x10AF
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-#define HDMI_FC_ISCR2_2 0x10B0
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-#define HDMI_FC_ISCR2_1 0x10B1
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-#define HDMI_FC_ISCR2_0 0x10B2
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-#define HDMI_FC_DATAUTO0 0x10B3
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-#define HDMI_FC_DATAUTO1 0x10B4
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-#define HDMI_FC_DATAUTO2 0x10B5
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-#define HDMI_FC_DATMAN 0x10B6
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-#define HDMI_FC_DATAUTO3 0x10B7
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-#define HDMI_FC_RDRB0 0x10B8
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-#define HDMI_FC_RDRB1 0x10B9
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-#define HDMI_FC_RDRB2 0x10BA
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-#define HDMI_FC_RDRB3 0x10BB
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-#define HDMI_FC_RDRB4 0x10BC
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-#define HDMI_FC_RDRB5 0x10BD
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-#define HDMI_FC_RDRB6 0x10BE
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-#define HDMI_FC_RDRB7 0x10BF
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-#define HDMI_FC_STAT0 0x10D0
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-#define HDMI_FC_INT0 0x10D1
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-#define HDMI_FC_MASK0 0x10D2
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-#define HDMI_FC_POL0 0x10D3
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-#define HDMI_FC_STAT1 0x10D4
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-#define HDMI_FC_INT1 0x10D5
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-#define HDMI_FC_MASK1 0x10D6
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-#define HDMI_FC_POL1 0x10D7
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-#define HDMI_FC_STAT2 0x10D8
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-#define HDMI_FC_INT2 0x10D9
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-#define HDMI_FC_MASK2 0x10DA
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-#define HDMI_FC_POL2 0x10DB
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-#define HDMI_FC_PRCONF 0x10E0
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-
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-#define HDMI_FC_GMD_STAT 0x1100
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-#define HDMI_FC_GMD_EN 0x1101
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-#define HDMI_FC_GMD_UP 0x1102
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-#define HDMI_FC_GMD_CONF 0x1103
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-#define HDMI_FC_GMD_HB 0x1104
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-#define HDMI_FC_GMD_PB0 0x1105
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-#define HDMI_FC_GMD_PB1 0x1106
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-#define HDMI_FC_GMD_PB2 0x1107
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-#define HDMI_FC_GMD_PB3 0x1108
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-#define HDMI_FC_GMD_PB4 0x1109
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-#define HDMI_FC_GMD_PB5 0x110A
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-#define HDMI_FC_GMD_PB6 0x110B
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-#define HDMI_FC_GMD_PB7 0x110C
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-#define HDMI_FC_GMD_PB8 0x110D
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-#define HDMI_FC_GMD_PB9 0x110E
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-#define HDMI_FC_GMD_PB10 0x110F
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-#define HDMI_FC_GMD_PB11 0x1110
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-#define HDMI_FC_GMD_PB12 0x1111
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-#define HDMI_FC_GMD_PB13 0x1112
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-#define HDMI_FC_GMD_PB14 0x1113
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-#define HDMI_FC_GMD_PB15 0x1114
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-#define HDMI_FC_GMD_PB16 0x1115
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-#define HDMI_FC_GMD_PB17 0x1116
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-#define HDMI_FC_GMD_PB18 0x1117
|
|
-#define HDMI_FC_GMD_PB19 0x1118
|
|
-#define HDMI_FC_GMD_PB20 0x1119
|
|
-#define HDMI_FC_GMD_PB21 0x111A
|
|
-#define HDMI_FC_GMD_PB22 0x111B
|
|
-#define HDMI_FC_GMD_PB23 0x111C
|
|
-#define HDMI_FC_GMD_PB24 0x111D
|
|
-#define HDMI_FC_GMD_PB25 0x111E
|
|
-#define HDMI_FC_GMD_PB26 0x111F
|
|
-#define HDMI_FC_GMD_PB27 0x1120
|
|
-
|
|
-#define HDMI_FC_DBGFORCE 0x1200
|
|
-#define HDMI_FC_DBGAUD0CH0 0x1201
|
|
-#define HDMI_FC_DBGAUD1CH0 0x1202
|
|
-#define HDMI_FC_DBGAUD2CH0 0x1203
|
|
-#define HDMI_FC_DBGAUD0CH1 0x1204
|
|
-#define HDMI_FC_DBGAUD1CH1 0x1205
|
|
-#define HDMI_FC_DBGAUD2CH1 0x1206
|
|
-#define HDMI_FC_DBGAUD0CH2 0x1207
|
|
-#define HDMI_FC_DBGAUD1CH2 0x1208
|
|
-#define HDMI_FC_DBGAUD2CH2 0x1209
|
|
-#define HDMI_FC_DBGAUD0CH3 0x120A
|
|
-#define HDMI_FC_DBGAUD1CH3 0x120B
|
|
-#define HDMI_FC_DBGAUD2CH3 0x120C
|
|
-#define HDMI_FC_DBGAUD0CH4 0x120D
|
|
-#define HDMI_FC_DBGAUD1CH4 0x120E
|
|
-#define HDMI_FC_DBGAUD2CH4 0x120F
|
|
-#define HDMI_FC_DBGAUD0CH5 0x1210
|
|
-#define HDMI_FC_DBGAUD1CH5 0x1211
|
|
-#define HDMI_FC_DBGAUD2CH5 0x1212
|
|
-#define HDMI_FC_DBGAUD0CH6 0x1213
|
|
-#define HDMI_FC_DBGAUD1CH6 0x1214
|
|
-#define HDMI_FC_DBGAUD2CH6 0x1215
|
|
-#define HDMI_FC_DBGAUD0CH7 0x1216
|
|
-#define HDMI_FC_DBGAUD1CH7 0x1217
|
|
-#define HDMI_FC_DBGAUD2CH7 0x1218
|
|
-#define HDMI_FC_DBGTMDS0 0x1219
|
|
-#define HDMI_FC_DBGTMDS1 0x121A
|
|
-#define HDMI_FC_DBGTMDS2 0x121B
|
|
+#define HDMI_FC_INVIDCONF 0x0040
|
|
+#define HDMI_FC_INHACTV0 0x0041
|
|
+#define HDMI_FC_INHACTV1 0x8040
|
|
+#define HDMI_FC_INHBLANK0 0x8041
|
|
+#define HDMI_FC_INHBLANK1 0x0042
|
|
+#define HDMI_FC_INVACTV0 0x0043
|
|
+#define HDMI_FC_INVACTV1 0x8042
|
|
+#define HDMI_FC_INVBLANK 0x8043
|
|
+#define HDMI_FC_HSYNCINDELAY0 0x4040
|
|
+#define HDMI_FC_HSYNCINDELAY1 0x4041
|
|
+#define HDMI_FC_HSYNCINWIDTH0 0xC040
|
|
+#define HDMI_FC_HSYNCINWIDTH1 0xC041
|
|
+#define HDMI_FC_VSYNCINDELAY 0x4042
|
|
+#define HDMI_FC_VSYNCINWIDTH 0x4043
|
|
+#define HDMI_FC_INFREQ0 0xC042
|
|
+#define HDMI_FC_INFREQ1 0xC043
|
|
+#define HDMI_FC_INFREQ2 0x0044
|
|
+#define HDMI_FC_CTRLDUR 0x0045
|
|
+#define HDMI_FC_EXCTRLDUR 0x8044
|
|
+#define HDMI_FC_EXCTRLSPAC 0x8045
|
|
+#define HDMI_FC_CH0PREAM 0x0046
|
|
+#define HDMI_FC_CH1PREAM 0x0047
|
|
+#define HDMI_FC_CH2PREAM 0x8046
|
|
+#define HDMI_FC_AVICONF3 0x8047
|
|
+#define HDMI_FC_GCP 0x4044
|
|
+#define HDMI_FC_AVICONF0 0x4045
|
|
+#define HDMI_FC_AVICONF1 0xC044
|
|
+#define HDMI_FC_AVICONF2 0xC045
|
|
+#define HDMI_FC_AVIVID 0x4046
|
|
+#define HDMI_FC_AVIETB0 0x4047
|
|
+#define HDMI_FC_AVIETB1 0xC046
|
|
+#define HDMI_FC_AVISBB0 0xC047
|
|
+#define HDMI_FC_AVISBB1 0x2040
|
|
+#define HDMI_FC_AVIELB0 0x2041
|
|
+#define HDMI_FC_AVIELB1 0xA040
|
|
+#define HDMI_FC_AVISRB0 0xA041
|
|
+#define HDMI_FC_AVISRB1 0x2042
|
|
+#define HDMI_FC_AUDICONF0 0x2043
|
|
+#define HDMI_FC_AUDICONF1 0xA042
|
|
+#define HDMI_FC_AUDICONF2 0xA043
|
|
+#define HDMI_FC_AUDICONF3 0x6040
|
|
+#define HDMI_FC_VSDIEEEID0 0x6041
|
|
+#define HDMI_FC_VSDSIZE 0xE040
|
|
+#define HDMI_FC_VSDIEEEID1 0x2044
|
|
+#define HDMI_FC_VSDIEEEID2 0x2045
|
|
+#define HDMI_FC_VSDPAYLOAD0 0xA044
|
|
+#define HDMI_FC_VSDPAYLOAD1 0xA045
|
|
+#define HDMI_FC_VSDPAYLOAD2 0x2046
|
|
+#define HDMI_FC_VSDPAYLOAD3 0x2047
|
|
+#define HDMI_FC_VSDPAYLOAD4 0xA046
|
|
+#define HDMI_FC_VSDPAYLOAD5 0xA047
|
|
+#define HDMI_FC_VSDPAYLOAD6 0x6044
|
|
+#define HDMI_FC_VSDPAYLOAD7 0x6045
|
|
+#define HDMI_FC_VSDPAYLOAD8 0xE044
|
|
+#define HDMI_FC_VSDPAYLOAD9 0xE045
|
|
+#define HDMI_FC_VSDPAYLOAD10 0x6046
|
|
+#define HDMI_FC_VSDPAYLOAD11 0x6047
|
|
+#define HDMI_FC_VSDPAYLOAD12 0xE046
|
|
+#define HDMI_FC_VSDPAYLOAD13 0xE047
|
|
+#define HDMI_FC_VSDPAYLOAD14 0x0048
|
|
+#define HDMI_FC_VSDPAYLOAD15 0x0049
|
|
+#define HDMI_FC_VSDPAYLOAD16 0x8048
|
|
+#define HDMI_FC_VSDPAYLOAD17 0x8049
|
|
+#define HDMI_FC_VSDPAYLOAD18 0x004A
|
|
+#define HDMI_FC_VSDPAYLOAD19 0x004B
|
|
+#define HDMI_FC_VSDPAYLOAD20 0x804A
|
|
+#define HDMI_FC_VSDPAYLOAD21 0x804B
|
|
+#define HDMI_FC_VSDPAYLOAD22 0x4048
|
|
+#define HDMI_FC_VSDPAYLOAD23 0x4049
|
|
+#define HDMI_FC_SPDVENDORNAME0 0xC048
|
|
+#define HDMI_FC_SPDVENDORNAME1 0xC049
|
|
+#define HDMI_FC_SPDVENDORNAME2 0x404A
|
|
+#define HDMI_FC_SPDVENDORNAME3 0x404B
|
|
+#define HDMI_FC_SPDVENDORNAME4 0xC04A
|
|
+#define HDMI_FC_SPDVENDORNAME5 0xC04B
|
|
+#define HDMI_FC_SPDVENDORNAME6 0x004C
|
|
+#define HDMI_FC_SPDVENDORNAME7 0x004D
|
|
+#define HDMI_FC_SDPPRODUCTNAME0 0x804C
|
|
+#define HDMI_FC_SDPPRODUCTNAME1 0x804D
|
|
+#define HDMI_FC_SDPPRODUCTNAME2 0x004E
|
|
+#define HDMI_FC_SDPPRODUCTNAME3 0x004F
|
|
+#define HDMI_FC_SDPPRODUCTNAME4 0x804E
|
|
+#define HDMI_FC_SDPPRODUCTNAME5 0x804F
|
|
+#define HDMI_FC_SDPPRODUCTNAME6 0x404C
|
|
+#define HDMI_FC_SDPPRODUCTNAME7 0x404D
|
|
+#define HDMI_FC_SDPPRODUCTNAME8 0xC04C
|
|
+#define HDMI_FC_SDPPRODUCTNAME9 0xC04D
|
|
+#define HDMI_FC_SDPPRODUCTNAME10 0x404E
|
|
+#define HDMI_FC_SDPPRODUCTNAME11 0x404F
|
|
+#define HDMI_FC_SDPPRODUCTNAME12 0xC04E
|
|
+#define HDMI_FC_SDPPRODUCTNAME13 0xC04F
|
|
+#define HDMI_FC_SDPPRODUCTNAME14 0x2048
|
|
+#define HDMI_FC_SPDPRODUCTNAME15 0x2049
|
|
+#define HDMI_FC_SPDDEVICEINF 0xA048
|
|
+#define HDMI_FC_AUDSCONF 0xA049
|
|
+#define HDMI_FC_AUDSSTAT 0x204A
|
|
+#define HDMI_FC_DATACH0FILL 0x204C
|
|
+#define HDMI_FC_DATACH1FILL 0x204D
|
|
+#define HDMI_FC_DATACH2FILL 0xA04C
|
|
+#define HDMI_FC_CTRLQHIGH 0xA04D
|
|
+#define HDMI_FC_CTRLQLOW 0x204E
|
|
+#define HDMI_FC_ACP0 0x204F
|
|
+#define HDMI_FC_ACP28 0xA04E
|
|
+#define HDMI_FC_ACP27 0xA04F
|
|
+#define HDMI_FC_ACP26 0x604C
|
|
+#define HDMI_FC_ACP25 0x604D
|
|
+#define HDMI_FC_ACP24 0xE04C
|
|
+#define HDMI_FC_ACP23 0xE04D
|
|
+#define HDMI_FC_ACP22 0x604E
|
|
+#define HDMI_FC_ACP21 0x604F
|
|
+#define HDMI_FC_ACP20 0xE04E
|
|
+#define HDMI_FC_ACP19 0xE04F
|
|
+#define HDMI_FC_ACP18 0x1040
|
|
+#define HDMI_FC_ACP17 0x1041
|
|
+#define HDMI_FC_ACP16 0x9040
|
|
+#define HDMI_FC_ACP15 0x9041
|
|
+#define HDMI_FC_ACP14 0x1042
|
|
+#define HDMI_FC_ACP13 0x1043
|
|
+#define HDMI_FC_ACP12 0x9042
|
|
+#define HDMI_FC_ACP11 0x9043
|
|
+#define HDMI_FC_ACP10 0x5040
|
|
+#define HDMI_FC_ACP9 0x5041
|
|
+#define HDMI_FC_ACP8 0xD040
|
|
+#define HDMI_FC_ACP7 0xD041
|
|
+#define HDMI_FC_ACP6 0x5042
|
|
+#define HDMI_FC_ACP5 0x5043
|
|
+#define HDMI_FC_ACP4 0xD042
|
|
+#define HDMI_FC_ACP3 0xD043
|
|
+#define HDMI_FC_ACP2 0x1044
|
|
+#define HDMI_FC_ACP1 0x1045
|
|
+#define HDMI_FC_ISCR1_0 0x9044
|
|
+#define HDMI_FC_ISCR1_16 0x9045
|
|
+#define HDMI_FC_ISCR1_15 0x1046
|
|
+#define HDMI_FC_ISCR1_14 0x1047
|
|
+#define HDMI_FC_ISCR1_13 0x9046
|
|
+#define HDMI_FC_ISCR1_12 0x9047
|
|
+#define HDMI_FC_ISCR1_11 0x5044
|
|
+#define HDMI_FC_ISCR1_10 0x5045
|
|
+#define HDMI_FC_ISCR1_9 0xD044
|
|
+#define HDMI_FC_ISCR1_8 0xD045
|
|
+#define HDMI_FC_ISCR1_7 0x5046
|
|
+#define HDMI_FC_ISCR1_6 0x5047
|
|
+#define HDMI_FC_ISCR1_5 0xD046
|
|
+#define HDMI_FC_ISCR1_4 0xD047
|
|
+#define HDMI_FC_ISCR1_3 0x3040
|
|
+#define HDMI_FC_ISCR1_2 0x3041
|
|
+#define HDMI_FC_ISCR1_1 0xB040
|
|
+#define HDMI_FC_ISCR2_15 0xB041
|
|
+#define HDMI_FC_ISCR2_14 0x3042
|
|
+#define HDMI_FC_ISCR2_13 0x3043
|
|
+#define HDMI_FC_ISCR2_12 0xB042
|
|
+#define HDMI_FC_ISCR2_11 0xB043
|
|
+#define HDMI_FC_ISCR2_10 0x7040
|
|
+#define HDMI_FC_ISCR2_9 0x7041
|
|
+#define HDMI_FC_ISCR2_8 0xF040
|
|
+#define HDMI_FC_ISCR2_7 0xF041
|
|
+#define HDMI_FC_ISCR2_6 0x7042
|
|
+#define HDMI_FC_ISCR2_5 0x7043
|
|
+#define HDMI_FC_ISCR2_4 0xF042
|
|
+#define HDMI_FC_ISCR2_3 0xF043
|
|
+#define HDMI_FC_ISCR2_2 0x3044
|
|
+#define HDMI_FC_ISCR2_1 0x3045
|
|
+#define HDMI_FC_ISCR2_0 0xB044
|
|
+#define HDMI_FC_DATAUTO0 0xB045
|
|
+#define HDMI_FC_DATAUTO1 0x3046
|
|
+#define HDMI_FC_DATAUTO2 0x3047
|
|
+#define HDMI_FC_DATMAN 0xB046
|
|
+#define HDMI_FC_DATAUTO3 0xB047
|
|
+#define HDMI_FC_RDRB0 0x7044
|
|
+#define HDMI_FC_RDRB1 0x7045
|
|
+#define HDMI_FC_RDRB2 0xF044
|
|
+#define HDMI_FC_RDRB3 0xF045
|
|
+#define HDMI_FC_RDRB4 0x7046
|
|
+#define HDMI_FC_RDRB5 0x7047
|
|
+#define HDMI_FC_RDRB6 0xF046
|
|
+#define HDMI_FC_RDRB7 0xF047
|
|
+#define HDMI_FC_STAT0 0x104C
|
|
+#define HDMI_FC_INT0 0x104D
|
|
+#define HDMI_FC_MASK0 0x904C
|
|
+#define HDMI_FC_POL0 0x904D
|
|
+#define HDMI_FC_STAT1 0x104E
|
|
+#define HDMI_FC_INT1 0x104F
|
|
+#define HDMI_FC_MASK1 0x904E
|
|
+#define HDMI_FC_POL1 0x904F
|
|
+#define HDMI_FC_STAT2 0x504C
|
|
+#define HDMI_FC_INT2 0x504D
|
|
+#define HDMI_FC_MASK2 0xD04C
|
|
+#define HDMI_FC_POL2 0xD04D
|
|
+#define HDMI_FC_PRCONF 0x3048
|
|
+
|
|
+#define HDMI_FC_GMD_STAT 0x0050
|
|
+#define HDMI_FC_GMD_EN 0x0051
|
|
+#define HDMI_FC_GMD_UP 0x8050
|
|
+#define HDMI_FC_GMD_CONF 0x8051
|
|
+#define HDMI_FC_GMD_HB 0x0052
|
|
+#define HDMI_FC_GMD_PB0 0x0053
|
|
+#define HDMI_FC_GMD_PB1 0x8052
|
|
+#define HDMI_FC_GMD_PB2 0x8053
|
|
+#define HDMI_FC_GMD_PB3 0x4050
|
|
+#define HDMI_FC_GMD_PB4 0x4051
|
|
+#define HDMI_FC_GMD_PB5 0xC050
|
|
+#define HDMI_FC_GMD_PB6 0xC051
|
|
+#define HDMI_FC_GMD_PB7 0x4052
|
|
+#define HDMI_FC_GMD_PB8 0x4053
|
|
+#define HDMI_FC_GMD_PB9 0xC052
|
|
+#define HDMI_FC_GMD_PB10 0xC053
|
|
+#define HDMI_FC_GMD_PB11 0x0054
|
|
+#define HDMI_FC_GMD_PB12 0x0055
|
|
+#define HDMI_FC_GMD_PB13 0x8054
|
|
+#define HDMI_FC_GMD_PB14 0x8055
|
|
+#define HDMI_FC_GMD_PB15 0x0056
|
|
+#define HDMI_FC_GMD_PB16 0x0057
|
|
+#define HDMI_FC_GMD_PB17 0x8056
|
|
+#define HDMI_FC_GMD_PB18 0x8057
|
|
+#define HDMI_FC_GMD_PB19 0x4054
|
|
+#define HDMI_FC_GMD_PB20 0x4055
|
|
+#define HDMI_FC_GMD_PB21 0xC054
|
|
+#define HDMI_FC_GMD_PB22 0xC055
|
|
+#define HDMI_FC_GMD_PB23 0x4056
|
|
+#define HDMI_FC_GMD_PB24 0x4057
|
|
+#define HDMI_FC_GMD_PB25 0xC056
|
|
+#define HDMI_FC_GMD_PB26 0xC057
|
|
+#define HDMI_FC_GMD_PB27 0x2050
|
|
+
|
|
+#define HDMI_FC_DBGFORCE 0x0840
|
|
+#define HDMI_FC_DBGAUD0CH0 0x0841
|
|
+#define HDMI_FC_DBGAUD1CH0 0x8840
|
|
+#define HDMI_FC_DBGAUD2CH0 0x8841
|
|
+#define HDMI_FC_DBGAUD0CH1 0x0842
|
|
+#define HDMI_FC_DBGAUD1CH1 0x0843
|
|
+#define HDMI_FC_DBGAUD2CH1 0x8842
|
|
+#define HDMI_FC_DBGAUD0CH2 0x8843
|
|
+#define HDMI_FC_DBGAUD1CH2 0x4840
|
|
+#define HDMI_FC_DBGAUD2CH2 0x4841
|
|
+#define HDMI_FC_DBGAUD0CH3 0xC840
|
|
+#define HDMI_FC_DBGAUD1CH3 0xC841
|
|
+#define HDMI_FC_DBGAUD2CH3 0x4842
|
|
+#define HDMI_FC_DBGAUD0CH4 0x4843
|
|
+#define HDMI_FC_DBGAUD1CH4 0xC842
|
|
+#define HDMI_FC_DBGAUD2CH4 0xC843
|
|
+#define HDMI_FC_DBGAUD0CH5 0x0844
|
|
+#define HDMI_FC_DBGAUD1CH5 0x0845
|
|
+#define HDMI_FC_DBGAUD2CH5 0x8844
|
|
+#define HDMI_FC_DBGAUD0CH6 0x8845
|
|
+#define HDMI_FC_DBGAUD1CH6 0x0846
|
|
+#define HDMI_FC_DBGAUD2CH6 0x0847
|
|
+#define HDMI_FC_DBGAUD0CH7 0x8846
|
|
+#define HDMI_FC_DBGAUD1CH7 0x8847
|
|
+#define HDMI_FC_DBGAUD2CH7 0x4844
|
|
+#define HDMI_FC_DBGTMDS0 0x4845
|
|
+#define HDMI_FC_DBGTMDS1 0xC844
|
|
+#define HDMI_FC_DBGTMDS2 0xC845
|
|
|
|
/* HDMI Source PHY Registers */
|
|
-#define HDMI_PHY_CONF0 0x3000
|
|
-#define HDMI_PHY_TST0 0x3001
|
|
-#define HDMI_PHY_TST1 0x3002
|
|
-#define HDMI_PHY_TST2 0x3003
|
|
-#define HDMI_PHY_STAT0 0x3004
|
|
-#define HDMI_PHY_INT0 0x3005
|
|
-#define HDMI_PHY_MASK0 0x3006
|
|
-#define HDMI_PHY_POL0 0x3007
|
|
+#define HDMI_PHY_CONF0 0x0240
|
|
+#define HDMI_PHY_TST0 0x0241
|
|
+#define HDMI_PHY_TST1 0x8240
|
|
+#define HDMI_PHY_TST2 0x8241
|
|
+#define HDMI_PHY_STAT0 0x0242
|
|
+#define HDMI_PHY_INT0 0x0243
|
|
+#define HDMI_PHY_MASK0 0x8242
|
|
+#define HDMI_PHY_POL0 0x8243
|
|
|
|
/* HDMI Master PHY Registers */
|
|
-#define HDMI_PHY_I2CM_SLAVE_ADDR 0x3020
|
|
-#define HDMI_PHY_I2CM_ADDRESS_ADDR 0x3021
|
|
-#define HDMI_PHY_I2CM_DATAO_1_ADDR 0x3022
|
|
-#define HDMI_PHY_I2CM_DATAO_0_ADDR 0x3023
|
|
-#define HDMI_PHY_I2CM_DATAI_1_ADDR 0x3024
|
|
-#define HDMI_PHY_I2CM_DATAI_0_ADDR 0x3025
|
|
-#define HDMI_PHY_I2CM_OPERATION_ADDR 0x3026
|
|
-#define HDMI_PHY_I2CM_INT_ADDR 0x3027
|
|
-#define HDMI_PHY_I2CM_CTLINT_ADDR 0x3028
|
|
-#define HDMI_PHY_I2CM_DIV_ADDR 0x3029
|
|
-#define HDMI_PHY_I2CM_SOFTRSTZ_ADDR 0x302a
|
|
-#define HDMI_PHY_I2CM_SS_SCL_HCNT_1_ADDR 0x302b
|
|
-#define HDMI_PHY_I2CM_SS_SCL_HCNT_0_ADDR 0x302c
|
|
-#define HDMI_PHY_I2CM_SS_SCL_LCNT_1_ADDR 0x302d
|
|
-#define HDMI_PHY_I2CM_SS_SCL_LCNT_0_ADDR 0x302e
|
|
-#define HDMI_PHY_I2CM_FS_SCL_HCNT_1_ADDR 0x302f
|
|
-#define HDMI_PHY_I2CM_FS_SCL_HCNT_0_ADDR 0x3030
|
|
-#define HDMI_PHY_I2CM_FS_SCL_LCNT_1_ADDR 0x3031
|
|
-#define HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR 0x3032
|
|
+#define HDMI_PHY_I2CM_SLAVE_ADDR 0x2240
|
|
+#define HDMI_PHY_I2CM_ADDRESS_ADDR 0x2241
|
|
+#define HDMI_PHY_I2CM_DATAO_1_ADDR 0xA240
|
|
+#define HDMI_PHY_I2CM_DATAO_0_ADDR 0xA241
|
|
+#define HDMI_PHY_I2CM_DATAI_1_ADDR 0x2242
|
|
+#define HDMI_PHY_I2CM_DATAI_0_ADDR 0x2243
|
|
+#define HDMI_PHY_I2CM_OPERATION_ADDR 0xA242
|
|
+#define HDMI_PHY_I2CM_INT_ADDR 0xA243
|
|
+#define HDMI_PHY_I2CM_CTLINT_ADDR 0x6240
|
|
+#define HDMI_PHY_I2CM_DIV_ADDR 0x6241
|
|
+#define HDMI_PHY_I2CM_SOFTRSTZ_ADDR 0xE240
|
|
+#define HDMI_PHY_I2CM_SS_SCL_HCNT_1_ADDR 0xE241
|
|
+#define HDMI_PHY_I2CM_SS_SCL_HCNT_0_ADDR 0x6242
|
|
+#define HDMI_PHY_I2CM_SS_SCL_LCNT_1_ADDR 0x6243
|
|
+#define HDMI_PHY_I2CM_SS_SCL_LCNT_0_ADDR 0xE242
|
|
+#define HDMI_PHY_I2CM_FS_SCL_HCNT_1_ADDR 0xE243
|
|
+#define HDMI_PHY_I2CM_FS_SCL_HCNT_0_ADDR 0x2244
|
|
+#define HDMI_PHY_I2CM_FS_SCL_LCNT_1_ADDR 0x2245
|
|
+#define HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR 0xA244
|
|
|
|
/* Audio Sampler Registers */
|
|
-#define HDMI_AUD_CONF0 0x3100
|
|
-#define HDMI_AUD_CONF1 0x3101
|
|
-#define HDMI_AUD_INT 0x3102
|
|
-#define HDMI_AUD_CONF2 0x3103
|
|
-#define HDMI_AUD_N1 0x3200
|
|
-#define HDMI_AUD_N2 0x3201
|
|
-#define HDMI_AUD_N3 0x3202
|
|
-#define HDMI_AUD_CTS1 0x3203
|
|
-#define HDMI_AUD_CTS2 0x3204
|
|
-#define HDMI_AUD_CTS3 0x3205
|
|
-#define HDMI_AUD_INPUTCLKFS 0x3206
|
|
-#define HDMI_AUD_SPDIFINT 0x3302
|
|
-#define HDMI_AUD_CONF0_HBR 0x3400
|
|
-#define HDMI_AUD_HBR_STATUS 0x3401
|
|
-#define HDMI_AUD_HBR_INT 0x3402
|
|
-#define HDMI_AUD_HBR_POL 0x3403
|
|
-#define HDMI_AUD_HBR_MASK 0x3404
|
|
+#define HDMI_AUD_CONF0 0x0250
|
|
+#define HDMI_AUD_CONF1 0x0251
|
|
+#define HDMI_AUD_INT 0x8250
|
|
+#define HDMI_AUD_CONF2 0x8251
|
|
+#define HDMI_AUD_N1 0x0A40
|
|
+#define HDMI_AUD_N2 0x0A41
|
|
+#define HDMI_AUD_N3 0x8A40
|
|
+#define HDMI_AUD_CTS1 0x8A41
|
|
+#define HDMI_AUD_CTS2 0x0A42
|
|
+#define HDMI_AUD_CTS3 0x0A43
|
|
+#define HDMI_AUD_INPUTCLKFS 0x8A42
|
|
+#define HDMI_AUD_SPDIFINT 0x8A50
|
|
+#define HDMI_AUD_CONF0_HBR 0x0260
|
|
+#define HDMI_AUD_HBR_STATUS 0x0261
|
|
+#define HDMI_AUD_HBR_INT 0x8260
|
|
+#define HDMI_AUD_HBR_POL 0x8261
|
|
+#define HDMI_AUD_HBR_MASK 0x0262
|
|
|
|
/* Generic Parallel Audio Interface Registers */
|
|
/* Not used as GPAUD interface is not enabled in hw */
|
|
-#define HDMI_GP_CONF0 0x3500
|
|
-#define HDMI_GP_CONF1 0x3501
|
|
-#define HDMI_GP_CONF2 0x3502
|
|
-#define HDMI_GP_STAT 0x3503
|
|
-#define HDMI_GP_INT 0x3504
|
|
-#define HDMI_GP_MASK 0x3505
|
|
-#define HDMI_GP_POL 0x3506
|
|
+#define HDMI_GP_CONF0 0x0270
|
|
+#define HDMI_GP_CONF1 0x0271
|
|
+#define HDMI_GP_CONF2 0x8270
|
|
+#define HDMI_GP_STAT 0x8271
|
|
+#define HDMI_GP_INT 0x0272
|
|
+#define HDMI_GP_MASK 0x0273
|
|
+#define HDMI_GP_POL 0x8272
|
|
|
|
/* Audio DMA Registers */
|
|
-#define HDMI_AHB_DMA_CONF0 0x3600
|
|
-#define HDMI_AHB_DMA_START 0x3601
|
|
-#define HDMI_AHB_DMA_STOP 0x3602
|
|
-#define HDMI_AHB_DMA_THRSLD 0x3603
|
|
-#define HDMI_AHB_DMA_STRADDR0 0x3604
|
|
-#define HDMI_AHB_DMA_STRADDR1 0x3605
|
|
-#define HDMI_AHB_DMA_STRADDR2 0x3606
|
|
-#define HDMI_AHB_DMA_STRADDR3 0x3607
|
|
-#define HDMI_AHB_DMA_STPADDR0 0x3608
|
|
-#define HDMI_AHB_DMA_STPADDR1 0x3609
|
|
-#define HDMI_AHB_DMA_STPADDR2 0x360a
|
|
-#define HDMI_AHB_DMA_STPADDR3 0x360b
|
|
-#define HDMI_AHB_DMA_BSTADDR0 0x360c
|
|
-#define HDMI_AHB_DMA_BSTADDR1 0x360d
|
|
-#define HDMI_AHB_DMA_BSTADDR2 0x360e
|
|
-#define HDMI_AHB_DMA_BSTADDR3 0x360f
|
|
-#define HDMI_AHB_DMA_MBLENGTH0 0x3610
|
|
-#define HDMI_AHB_DMA_MBLENGTH1 0x3611
|
|
-#define HDMI_AHB_DMA_STAT 0x3612
|
|
-#define HDMI_AHB_DMA_INT 0x3613
|
|
-#define HDMI_AHB_DMA_MASK 0x3614
|
|
-#define HDMI_AHB_DMA_POL 0x3615
|
|
-#define HDMI_AHB_DMA_CONF1 0x3616
|
|
-#define HDMI_AHB_DMA_BUFFSTAT 0x3617
|
|
-#define HDMI_AHB_DMA_BUFFINT 0x3618
|
|
-#define HDMI_AHB_DMA_BUFFMASK 0x3619
|
|
-#define HDMI_AHB_DMA_BUFFPOL 0x361a
|
|
+#define HDMI_AHB_DMA_CONF0 0x0A60
|
|
+#define HDMI_AHB_DMA_START 0x0A61
|
|
+#define HDMI_AHB_DMA_STOP 0x8A60
|
|
+#define HDMI_AHB_DMA_THRSLD 0x8A61
|
|
+#define HDMI_AHB_DMA_STRADDR0 0x0A62
|
|
+#define HDMI_AHB_DMA_STRADDR1 0x0A63
|
|
+#define HDMI_AHB_DMA_STRADDR2 0x8A62
|
|
+#define HDMI_AHB_DMA_STRADDR3 0x8A63
|
|
+#define HDMI_AHB_DMA_STPADDR0 0x4A60
|
|
+#define HDMI_AHB_DMA_STPADDR1 0x4A61
|
|
+#define HDMI_AHB_DMA_STPADDR2 0xCA60
|
|
+#define HDMI_AHB_DMA_STPADDR3 0xCA61
|
|
+#define HDMI_AHB_DMA_BSTADDR0 0x4A62
|
|
+#define HDMI_AHB_DMA_BSTADDR1 0x4A63
|
|
+#define HDMI_AHB_DMA_BSTADDR2 0xCA62
|
|
+#define HDMI_AHB_DMA_BSTADDR3 0xCA63
|
|
+#define HDMI_AHB_DMA_MBLENGTH0 0x0A64
|
|
+#define HDMI_AHB_DMA_MBLENGTH1 0x0A65
|
|
+#define HDMI_AHB_DMA_STAT 0x8A64
|
|
+#define HDMI_AHB_DMA_INT 0x8A65
|
|
+#define HDMI_AHB_DMA_MASK 0x0A66
|
|
+#define HDMI_AHB_DMA_POL 0x0A67
|
|
+#define HDMI_AHB_DMA_CONF1 0x8A66
|
|
+#define HDMI_AHB_DMA_BUFFSTAT 0x8A67
|
|
+#define HDMI_AHB_DMA_BUFFINT 0x4A64
|
|
+#define HDMI_AHB_DMA_BUFFMASK 0x4A65
|
|
+#define HDMI_AHB_DMA_BUFFPOL 0xCA64
|
|
|
|
/* Main Controller Registers */
|
|
-#define HDMI_MC_SFRDIV 0x4000
|
|
-#define HDMI_MC_CLKDIS 0x4001
|
|
-#define HDMI_MC_SWRSTZ 0x4002
|
|
-#define HDMI_MC_OPCTRL 0x4003
|
|
-#define HDMI_MC_FLOWCTRL 0x4004
|
|
-#define HDMI_MC_PHYRSTZ 0x4005
|
|
-#define HDMI_MC_LOCKONCLOCK 0x4006
|
|
-#define HDMI_MC_HEACPHY_RST 0x4007
|
|
+#define HDMI_MC_SFRDIV 0x0080
|
|
+#define HDMI_MC_CLKDIS 0x0081
|
|
+#define HDMI_MC_SWRSTZ 0x8080
|
|
+#define HDMI_MC_OPCTRL 0x8081
|
|
+#define HDMI_MC_FLOWCTRL 0x0082
|
|
+#define HDMI_MC_PHYRSTZ 0x0083
|
|
+#define HDMI_MC_LOCKONCLOCK 0x8082
|
|
+#define HDMI_MC_HEACPHY_RST 0x8083
|
|
|
|
/* Color Space Converter Registers */
|
|
-#define HDMI_CSC_CFG 0x4100
|
|
-#define HDMI_CSC_SCALE 0x4101
|
|
-#define HDMI_CSC_COEF_A1_MSB 0x4102
|
|
-#define HDMI_CSC_COEF_A1_LSB 0x4103
|
|
-#define HDMI_CSC_COEF_A2_MSB 0x4104
|
|
-#define HDMI_CSC_COEF_A2_LSB 0x4105
|
|
-#define HDMI_CSC_COEF_A3_MSB 0x4106
|
|
-#define HDMI_CSC_COEF_A3_LSB 0x4107
|
|
-#define HDMI_CSC_COEF_A4_MSB 0x4108
|
|
-#define HDMI_CSC_COEF_A4_LSB 0x4109
|
|
-#define HDMI_CSC_COEF_B1_MSB 0x410A
|
|
-#define HDMI_CSC_COEF_B1_LSB 0x410B
|
|
-#define HDMI_CSC_COEF_B2_MSB 0x410C
|
|
-#define HDMI_CSC_COEF_B2_LSB 0x410D
|
|
-#define HDMI_CSC_COEF_B3_MSB 0x410E
|
|
-#define HDMI_CSC_COEF_B3_LSB 0x410F
|
|
-#define HDMI_CSC_COEF_B4_MSB 0x4110
|
|
-#define HDMI_CSC_COEF_B4_LSB 0x4111
|
|
-#define HDMI_CSC_COEF_C1_MSB 0x4112
|
|
-#define HDMI_CSC_COEF_C1_LSB 0x4113
|
|
-#define HDMI_CSC_COEF_C2_MSB 0x4114
|
|
-#define HDMI_CSC_COEF_C2_LSB 0x4115
|
|
-#define HDMI_CSC_COEF_C3_MSB 0x4116
|
|
-#define HDMI_CSC_COEF_C3_LSB 0x4117
|
|
-#define HDMI_CSC_COEF_C4_MSB 0x4118
|
|
-#define HDMI_CSC_COEF_C4_LSB 0x4119
|
|
+#define HDMI_CSC_CFG 0x0090
|
|
+#define HDMI_CSC_SCALE 0x0091
|
|
+#define HDMI_CSC_COEF_A1_MSB 0x8090
|
|
+#define HDMI_CSC_COEF_A1_LSB 0x8091
|
|
+#define HDMI_CSC_COEF_A2_MSB 0x0092
|
|
+#define HDMI_CSC_COEF_A2_LSB 0x0093
|
|
+#define HDMI_CSC_COEF_A3_MSB 0x8092
|
|
+#define HDMI_CSC_COEF_A3_LSB 0x8093
|
|
+#define HDMI_CSC_COEF_A4_MSB 0x4090
|
|
+#define HDMI_CSC_COEF_A4_LSB 0x4091
|
|
+#define HDMI_CSC_COEF_B1_MSB 0xC090
|
|
+#define HDMI_CSC_COEF_B1_LSB 0xC091
|
|
+#define HDMI_CSC_COEF_B2_MSB 0x4092
|
|
+#define HDMI_CSC_COEF_B2_LSB 0x4093
|
|
+#define HDMI_CSC_COEF_B3_MSB 0xC092
|
|
+#define HDMI_CSC_COEF_B3_LSB 0xC093
|
|
+#define HDMI_CSC_COEF_B4_MSB 0x0094
|
|
+#define HDMI_CSC_COEF_B4_LSB 0x0095
|
|
+#define HDMI_CSC_COEF_C1_MSB 0x8094
|
|
+#define HDMI_CSC_COEF_C1_LSB 0x8095
|
|
+#define HDMI_CSC_COEF_C2_MSB 0x0096
|
|
+#define HDMI_CSC_COEF_C2_LSB 0x0097
|
|
+#define HDMI_CSC_COEF_C3_MSB 0x8096
|
|
+#define HDMI_CSC_COEF_C3_LSB 0x8097
|
|
+#define HDMI_CSC_COEF_C4_MSB 0x4094
|
|
+#define HDMI_CSC_COEF_C4_LSB 0x4095
|
|
|
|
/* HDCP Encryption Engine Registers */
|
|
-#define HDMI_A_HDCPCFG0 0x5000
|
|
-#define HDMI_A_HDCPCFG1 0x5001
|
|
-#define HDMI_A_HDCPOBS0 0x5002
|
|
-#define HDMI_A_HDCPOBS1 0x5003
|
|
-#define HDMI_A_HDCPOBS2 0x5004
|
|
-#define HDMI_A_HDCPOBS3 0x5005
|
|
-#define HDMI_A_APIINTCLR 0x5006
|
|
-#define HDMI_A_APIINTSTAT 0x5007
|
|
-#define HDMI_A_APIINTMSK 0x5008
|
|
-#define HDMI_A_VIDPOLCFG 0x5009
|
|
-#define HDMI_A_OESSWCFG 0x500A
|
|
-#define HDMI_A_TIMER1SETUP0 0x500B
|
|
-#define HDMI_A_TIMER1SETUP1 0x500C
|
|
-#define HDMI_A_TIMER2SETUP0 0x500D
|
|
-#define HDMI_A_TIMER2SETUP1 0x500E
|
|
-#define HDMI_A_100MSCFG 0x500F
|
|
-#define HDMI_A_2SCFG0 0x5010
|
|
-#define HDMI_A_2SCFG1 0x5011
|
|
-#define HDMI_A_5SCFG0 0x5012
|
|
-#define HDMI_A_5SCFG1 0x5013
|
|
-#define HDMI_A_SRMVERLSB 0x5014
|
|
-#define HDMI_A_SRMVERMSB 0x5015
|
|
-#define HDMI_A_SRMCTRL 0x5016
|
|
-#define HDMI_A_SFRSETUP 0x5017
|
|
-#define HDMI_A_I2CHSETUP 0x5018
|
|
-#define HDMI_A_INTSETUP 0x5019
|
|
-#define HDMI_A_PRESETUP 0x501A
|
|
-#define HDMI_A_SRM_BASE 0x5020
|
|
+#define HDMI_A_HDCPCFG0 0x00C0
|
|
+#define HDMI_A_HDCPCFG1 0x00C1
|
|
+#define HDMI_A_HDCPOBS0 0x80C0
|
|
+#define HDMI_A_HDCPOBS1 0x80C1
|
|
+#define HDMI_A_HDCPOBS2 0x00C2
|
|
+#define HDMI_A_HDCPOBS3 0x00C3
|
|
+#define HDMI_A_APIINTCLR 0x80C2
|
|
+#define HDMI_A_APIINTSTAT 0x80C3
|
|
+#define HDMI_A_APIINTMSK 0x40C0
|
|
+#define HDMI_A_VIDPOLCFG 0x40C1
|
|
+#define HDMI_A_OESSWCFG 0xC0C0
|
|
+#define HDMI_A_TIMER1SETUP0 0xC0C1
|
|
+#define HDMI_A_TIMER1SETUP1 0x40C2
|
|
+#define HDMI_A_TIMER2SETUP0 0x40C3
|
|
+#define HDMI_A_TIMER2SETUP1 0xC0C2
|
|
+#define HDMI_A_100MSCFG 0xC0C3
|
|
+#define HDMI_A_2SCFG0 0x00C4
|
|
+#define HDMI_A_2SCFG1 0x00C5
|
|
+#define HDMI_A_5SCFG0 0x80C4
|
|
+#define HDMI_A_5SCFG1 0x80C5
|
|
+#define HDMI_A_SRMVERLSB 0x00C6
|
|
+#define HDMI_A_SRMVERMSB 0x00C7
|
|
+#define HDMI_A_SRMCTRL 0x80C6
|
|
+#define HDMI_A_SFRSETUP 0x80C7
|
|
+#define HDMI_A_I2CHSETUP 0x40C4
|
|
+#define HDMI_A_INTSETUP 0x40C5
|
|
+#define HDMI_A_PRESETUP 0xC0C4
|
|
+#define HDMI_A_SRM_BASE 0x20C0
|
|
|
|
/* CEC Engine Registers */
|
|
-#define HDMI_CEC_CTRL 0x7D00
|
|
-#define HDMI_CEC_STAT 0x7D01
|
|
-#define HDMI_CEC_MASK 0x7D02
|
|
-#define HDMI_CEC_POLARITY 0x7D03
|
|
-#define HDMI_CEC_INT 0x7D04
|
|
-#define HDMI_CEC_ADDR_L 0x7D05
|
|
-#define HDMI_CEC_ADDR_H 0x7D06
|
|
-#define HDMI_CEC_TX_CNT 0x7D07
|
|
-#define HDMI_CEC_RX_CNT 0x7D08
|
|
-#define HDMI_CEC_TX_DATA0 0x7D10
|
|
-#define HDMI_CEC_TX_DATA1 0x7D11
|
|
-#define HDMI_CEC_TX_DATA2 0x7D12
|
|
-#define HDMI_CEC_TX_DATA3 0x7D13
|
|
-#define HDMI_CEC_TX_DATA4 0x7D14
|
|
-#define HDMI_CEC_TX_DATA5 0x7D15
|
|
-#define HDMI_CEC_TX_DATA6 0x7D16
|
|
-#define HDMI_CEC_TX_DATA7 0x7D17
|
|
-#define HDMI_CEC_TX_DATA8 0x7D18
|
|
-#define HDMI_CEC_TX_DATA9 0x7D19
|
|
-#define HDMI_CEC_TX_DATA10 0x7D1a
|
|
-#define HDMI_CEC_TX_DATA11 0x7D1b
|
|
-#define HDMI_CEC_TX_DATA12 0x7D1c
|
|
-#define HDMI_CEC_TX_DATA13 0x7D1d
|
|
-#define HDMI_CEC_TX_DATA14 0x7D1e
|
|
-#define HDMI_CEC_TX_DATA15 0x7D1f
|
|
-#define HDMI_CEC_RX_DATA0 0x7D20
|
|
-#define HDMI_CEC_RX_DATA1 0x7D21
|
|
-#define HDMI_CEC_RX_DATA2 0x7D22
|
|
-#define HDMI_CEC_RX_DATA3 0x7D23
|
|
-#define HDMI_CEC_RX_DATA4 0x7D24
|
|
-#define HDMI_CEC_RX_DATA5 0x7D25
|
|
-#define HDMI_CEC_RX_DATA6 0x7D26
|
|
-#define HDMI_CEC_RX_DATA7 0x7D27
|
|
-#define HDMI_CEC_RX_DATA8 0x7D28
|
|
-#define HDMI_CEC_RX_DATA9 0x7D29
|
|
-#define HDMI_CEC_RX_DATA10 0x7D2a
|
|
-#define HDMI_CEC_RX_DATA11 0x7D2b
|
|
-#define HDMI_CEC_RX_DATA12 0x7D2c
|
|
-#define HDMI_CEC_RX_DATA13 0x7D2d
|
|
-#define HDMI_CEC_RX_DATA14 0x7D2e
|
|
-#define HDMI_CEC_RX_DATA15 0x7D2f
|
|
-#define HDMI_CEC_LOCK 0x7D30
|
|
-#define HDMI_CEC_WKUPCTRL 0x7D31
|
|
+#define HDMI_CEC_CTRL 0x06F0
|
|
+#define HDMI_CEC_STAT 0x06F1
|
|
+#define HDMI_CEC_MASK 0x86F0
|
|
+#define HDMI_CEC_POLARITY 0x86F1
|
|
+#define HDMI_CEC_INT 0x06F2
|
|
+#define HDMI_CEC_ADDR_L 0x06F3
|
|
+#define HDMI_CEC_ADDR_H 0x86F2
|
|
+#define HDMI_CEC_TX_CNT 0x86F3
|
|
+#define HDMI_CEC_RX_CNT 0x46F0
|
|
+#define HDMI_CEC_TX_DATA0 0x06F4
|
|
+#define HDMI_CEC_TX_DATA1 0x06F5
|
|
+#define HDMI_CEC_TX_DATA2 0x86F4
|
|
+#define HDMI_CEC_TX_DATA3 0x86F5
|
|
+#define HDMI_CEC_TX_DATA4 0x06F6
|
|
+#define HDMI_CEC_TX_DATA5 0x06F7
|
|
+#define HDMI_CEC_TX_DATA6 0x86F6
|
|
+#define HDMI_CEC_TX_DATA7 0x86F7
|
|
+#define HDMI_CEC_TX_DATA8 0x46F4
|
|
+#define HDMI_CEC_TX_DATA9 0x46F5
|
|
+#define HDMI_CEC_TX_DATA10 0xC6F4
|
|
+#define HDMI_CEC_TX_DATA11 0xC6F5
|
|
+#define HDMI_CEC_TX_DATA12 0x46F6
|
|
+#define HDMI_CEC_TX_DATA13 0x46F7
|
|
+#define HDMI_CEC_TX_DATA14 0xC6F6
|
|
+#define HDMI_CEC_TX_DATA15 0xC6F7
|
|
+#define HDMI_CEC_RX_DATA0 0x26F0
|
|
+#define HDMI_CEC_RX_DATA1 0x26F1
|
|
+#define HDMI_CEC_RX_DATA2 0xA6F0
|
|
+#define HDMI_CEC_RX_DATA3 0xA6F1
|
|
+#define HDMI_CEC_RX_DATA4 0x26F2
|
|
+#define HDMI_CEC_RX_DATA5 0x26F3
|
|
+#define HDMI_CEC_RX_DATA6 0xA6F2
|
|
+#define HDMI_CEC_RX_DATA7 0xA6F3
|
|
+#define HDMI_CEC_RX_DATA8 0x66F0
|
|
+#define HDMI_CEC_RX_DATA9 0x66F1
|
|
+#define HDMI_CEC_RX_DATA10 0xE6F0
|
|
+#define HDMI_CEC_RX_DATA11 0xE6F1
|
|
+#define HDMI_CEC_RX_DATA12 0x66F2
|
|
+#define HDMI_CEC_RX_DATA13 0x66F3
|
|
+#define HDMI_CEC_RX_DATA14 0xE6F2
|
|
+#define HDMI_CEC_RX_DATA15 0xE6F3
|
|
+#define HDMI_CEC_LOCK 0x26F4
|
|
+#define HDMI_CEC_WKUPCTRL 0x26F5
|
|
|
|
/* I2C Master Registers (E-DDC) */
|
|
-#define HDMI_I2CM_SLAVE 0x7E00
|
|
-#define HDMI_I2CM_ADDRESS 0x7E01
|
|
-#define HDMI_I2CM_DATAO 0x7E02
|
|
-#define HDMI_I2CM_DATAI 0x7E03
|
|
-#define HDMI_I2CM_OPERATION 0x7E04
|
|
-#define HDMI_I2CM_INT 0x7E05
|
|
-#define HDMI_I2CM_CTLINT 0x7E06
|
|
-#define HDMI_I2CM_DIV 0x7E07
|
|
-#define HDMI_I2CM_SEGADDR 0x7E08
|
|
-#define HDMI_I2CM_SOFTRSTZ 0x7E09
|
|
-#define HDMI_I2CM_SEGPTR 0x7E0A
|
|
-#define HDMI_I2CM_SS_SCL_HCNT_1_ADDR 0x7E0B
|
|
-#define HDMI_I2CM_SS_SCL_HCNT_0_ADDR 0x7E0C
|
|
-#define HDMI_I2CM_SS_SCL_LCNT_1_ADDR 0x7E0D
|
|
-#define HDMI_I2CM_SS_SCL_LCNT_0_ADDR 0x7E0E
|
|
-#define HDMI_I2CM_FS_SCL_HCNT_1_ADDR 0x7E0F
|
|
-#define HDMI_I2CM_FS_SCL_HCNT_0_ADDR 0x7E10
|
|
-#define HDMI_I2CM_FS_SCL_LCNT_1_ADDR 0x7E11
|
|
-#define HDMI_I2CM_FS_SCL_LCNT_0_ADDR 0x7E12
|
|
+#define HDMI_I2CM_SLAVE 0x0EE0
|
|
+#define HDMI_I2CM_ADDRESS 0x0EE1
|
|
+#define HDMI_I2CM_DATAO 0x8EE0
|
|
+#define HDMI_I2CM_DATAI 0x8EE1
|
|
+#define HDMI_I2CM_OPERATION 0x0EE2
|
|
+#define HDMI_I2CM_INT 0x0EE3
|
|
+#define HDMI_I2CM_CTLINT 0x8EE2
|
|
+#define HDMI_I2CM_DIV 0x8EE3
|
|
+#define HDMI_I2CM_SEGADDR 0x4EE0
|
|
+#define HDMI_I2CM_SOFTRSTZ 0x4EE1
|
|
+#define HDMI_I2CM_SEGPTR 0xCEE0
|
|
+#define HDMI_I2CM_SS_SCL_HCNT_1_ADDR 0xCEE1
|
|
+#define HDMI_I2CM_SS_SCL_HCNT_0_ADDR 0x4EE2
|
|
+#define HDMI_I2CM_SS_SCL_LCNT_1_ADDR 0x4EE3
|
|
+#define HDMI_I2CM_SS_SCL_LCNT_0_ADDR 0xCEE2
|
|
+#define HDMI_I2CM_FS_SCL_HCNT_1_ADDR 0xCEE3
|
|
+#define HDMI_I2CM_FS_SCL_HCNT_0_ADDR 0x0EE4
|
|
+#define HDMI_I2CM_FS_SCL_LCNT_1_ADDR 0x0EE5
|
|
+#define HDMI_I2CM_FS_SCL_LCNT_0_ADDR 0x8EE4
|
|
|
|
/* Random Number Generator Registers (RNG) */
|
|
-#define HDMI_RNG_BASE 0x8000
|
|
+#define HDMI_RNG_BASE 0x0100
|
|
|
|
|
|
/*
|
|
@@ -979,6 +979,7 @@ enum {
|
|
HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1,
|
|
|
|
/* MC_SWRSTZ field values */
|
|
+ HDMI_MC_SWRSTZ_CECSWRST_REQ = 0x40,
|
|
HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02,
|
|
|
|
/* MC_FLOWCTRL field values */
|
|
diff --git a/drivers/video/sunxi/disp2/hdmi/aw/hdmi_cec.c b/drivers/video/sunxi/disp2/hdmi/aw/hdmi_cec.c
|
|
index 8f06eb4..b407caf 100644
|
|
--- a/drivers/video/sunxi/disp2/hdmi/aw/hdmi_cec.c
|
|
+++ b/drivers/video/sunxi/disp2/hdmi/aw/hdmi_cec.c
|
|
@@ -42,14 +42,13 @@
|
|
#include <linux/module.h>
|
|
#include <linux/bitrev.h>
|
|
#include <linux/kthread.h>
|
|
-
|
|
#include <linux/console.h>
|
|
#include <linux/types.h>
|
|
|
|
#include "dw_hdmi.h"
|
|
#include "hdmi_cec.h"
|
|
#include "hdmi_edid.h"
|
|
-
|
|
+#include "../drv_hdmi_i.h"
|
|
|
|
#define MAX_MESSAGE_LEN 17
|
|
|
|
@@ -87,7 +86,6 @@ struct hdmi_cec_event {
|
|
struct list_head list;
|
|
};
|
|
|
|
-
|
|
static LIST_HEAD(head);
|
|
|
|
static int count_lo;
|
|
@@ -97,24 +95,27 @@ static int hdmi_cec_major;
|
|
static struct class *hdmi_cec_class;
|
|
static struct hdmi_cec_priv hdmi_cec_data;
|
|
static u8 open_count;
|
|
+static u8 cec_l_addr_l = 0, cec_l_addr_h = 0;
|
|
static wait_queue_head_t hdmi_cec_queue;
|
|
static wait_queue_head_t tx_cec_queue;
|
|
|
|
-/* FIXME : get base address from resource */
|
|
-static unsigned long hdmi_base = 0xf1ee0000;
|
|
+static int tx_reg[15] = {HDMI_CEC_TX_DATA0, HDMI_CEC_TX_DATA1, HDMI_CEC_TX_DATA2,\
|
|
+ HDMI_CEC_TX_DATA3, HDMI_CEC_TX_DATA4, HDMI_CEC_TX_DATA5,\
|
|
+ HDMI_CEC_TX_DATA6, HDMI_CEC_TX_DATA7, HDMI_CEC_TX_DATA8,\
|
|
+ HDMI_CEC_TX_DATA9, HDMI_CEC_TX_DATA10, HDMI_CEC_TX_DATA11,\
|
|
+ HDMI_CEC_TX_DATA12, HDMI_CEC_TX_DATA13, HDMI_CEC_TX_DATA14,\
|
|
+ HDMI_CEC_TX_DATA15};
|
|
|
|
+static int rx_reg[15] = {HDMI_CEC_RX_DATA0, HDMI_CEC_RX_DATA1, HDMI_CEC_RX_DATA2,\
|
|
+ HDMI_CEC_RX_DATA3, HDMI_CEC_RX_DATA4, HDMI_CEC_RX_DATA5,\
|
|
+ HDMI_CEC_RX_DATA6, HDMI_CEC_RX_DATA7, HDMI_CEC_RX_DATA8,\
|
|
+ HDMI_CEC_RX_DATA9, HDMI_CEC_RX_DATA10, HDMI_CEC_RX_DATA11,\
|
|
+ HDMI_CEC_RX_DATA12, HDMI_CEC_RX_DATA13, HDMI_CEC_RX_DATA14,\
|
|
+ HDMI_CEC_RX_DATA15};
|
|
|
|
-/* FIXME : calculate all register addresses in dw_hdmi.h and remove function */
|
|
-u32 dwc2sunxi(u32 addr)
|
|
-{
|
|
- u32 x = bitrev32((u32)addr) | (u32)addr; // put bit-reversed version in upper 16bit
|
|
- x = x & 0x55555555; // then extract all even bits
|
|
- x = (x | (x >> 1)) & 0x33333333; // and move them all to the lower 16bit
|
|
- x = (x | (x >> 2)) & 0x0f0f0f0f; // in multiple steps
|
|
- x = (x | (x >> 4)) & 0x00ff00ff; // ...
|
|
- x = (x | (x >> 8)) & 0x0000ffff;
|
|
- return (u32)x;
|
|
-}
|
|
+
|
|
+/* FIXME : get base address from resource */
|
|
+static unsigned long hdmi_base = 0xf1ee0000;
|
|
|
|
void hdmi_writel(u32 value, unsigned int reg)
|
|
{
|
|
@@ -135,16 +136,78 @@ u8 hdmi_readb(unsigned int reg)
|
|
|
|
/* unlock read access */
|
|
hdmi_writel(0x54524545, 0x10010);
|
|
- value = __raw_readb(hdmi_base + dwc2sunxi(reg));
|
|
+ value = __raw_readb(hdmi_base + reg);
|
|
return value;
|
|
}
|
|
|
|
void hdmi_writeb(u8 value, unsigned int reg)
|
|
{
|
|
- reg = dwc2sunxi(reg);
|
|
__raw_writeb(value, hdmi_base + reg);
|
|
}
|
|
|
|
+static int sunxi_hdmi_notify(struct notifier_block *nb,
|
|
+ unsigned long code, void *unused)
|
|
+{
|
|
+ u8 val = 0;
|
|
+ struct hdmi_cec_event *event = NULL;
|
|
+
|
|
+ if (open_count) {
|
|
+ switch (code) {
|
|
+ case 0x00: // Unplug
|
|
+ pr_err("HDMI link disconnected\n");
|
|
+ event = vmalloc(sizeof(struct hdmi_cec_event));
|
|
+ if (NULL == event) {
|
|
+ pr_err("%s: Not enough memory!\n", __func__);
|
|
+ break;
|
|
+ }
|
|
+ memset(event, 0, sizeof(struct hdmi_cec_event));
|
|
+ event->event_type = MESSAGE_TYPE_DISCONNECTED;
|
|
+ mutex_lock(&hdmi_cec_data.lock);
|
|
+ list_add_tail(&event->list, &head);
|
|
+ mutex_unlock(&hdmi_cec_data.lock);
|
|
+ wake_up(&hdmi_cec_queue);
|
|
+ break;
|
|
+ case 0x04: // Plug
|
|
+ pr_err("HDMI link connected\n");
|
|
+ event = vmalloc(sizeof(struct hdmi_cec_event));
|
|
+ if (NULL == event) {
|
|
+ pr_err("%s: Not enough memory\n", __func__);
|
|
+ break;
|
|
+ }
|
|
+ memset(event, 0, sizeof(struct hdmi_cec_event));
|
|
+ event->event_type = MESSAGE_TYPE_CONNECTED;
|
|
+ mutex_lock(&hdmi_cec_data.lock);
|
|
+ list_add_tail(&event->list, &head);
|
|
+ mutex_unlock(&hdmi_cec_data.lock);
|
|
+ wake_up(&hdmi_cec_queue);
|
|
+ break;
|
|
+ case 0x05: // reinit done
|
|
+ pr_err("HDMI reinitialized\n");
|
|
+ val = hdmi_readb(HDMI_MC_CLKDIS);
|
|
+ val &= ~HDMI_MC_CLKDIS_CECCLK_DISABLE;
|
|
+ hdmi_writeb(val, HDMI_MC_CLKDIS);
|
|
+ hdmi_writeb(0x02, HDMI_CEC_CTRL);
|
|
+ /* enable CEC receive */
|
|
+ hdmi_writel(0x84, 0x1003c);
|
|
+ /* Force read unlock */
|
|
+ hdmi_writeb(0x0, HDMI_CEC_LOCK);
|
|
+ val = HDMI_IH_CEC_STAT0_ERROR_INIT | HDMI_IH_CEC_STAT0_NACK | HDMI_IH_CEC_STAT0_EOM | HDMI_IH_CEC_STAT0_DONE;
|
|
+ hdmi_writeb(val, HDMI_CEC_POLARITY);
|
|
+ val = HDMI_IH_CEC_STAT0_WAKEUP | HDMI_IH_CEC_STAT0_ERROR_FOLL | HDMI_IH_CEC_STAT0_ARB_LOST;
|
|
+ hdmi_writeb(val, HDMI_CEC_MASK);
|
|
+ hdmi_writeb(val, HDMI_IH_MUTE_CEC_STAT0);
|
|
+ hdmi_writeb(cec_l_addr_l, HDMI_CEC_ADDR_L);
|
|
+ hdmi_writeb(cec_l_addr_h, HDMI_CEC_ADDR_H);
|
|
+ break;
|
|
+ }
|
|
+ }
|
|
+ return NOTIFY_DONE;
|
|
+}
|
|
+
|
|
+static struct notifier_block sunxi_hdmi_nb = {
|
|
+ .notifier_call = sunxi_hdmi_notify,
|
|
+};
|
|
+
|
|
static void initialize_hdmi_ih_mutes(void)
|
|
{
|
|
u8 ih_mute;
|
|
@@ -296,7 +359,6 @@ int rxack_thread(void *data)
|
|
{
|
|
return 0;
|
|
}
|
|
-
|
|
usleep_range(1600, 1700);
|
|
}
|
|
}
|
|
@@ -362,7 +424,7 @@ void hdmi_cec_handle(u16 cec_stat)
|
|
}
|
|
event->event_type = MESSAGE_TYPE_RECEIVE_SUCCESS;
|
|
for (i = 0; i < event->msg_len; i++)
|
|
- event->msg[i] = hdmi_readb(HDMI_CEC_RX_DATA0+i);
|
|
+ event->msg[i] = hdmi_readb(rx_reg[i]);
|
|
hdmi_writeb(0x0, HDMI_CEC_LOCK);
|
|
mutex_lock(&hdmi_cec_data.lock);
|
|
list_add_tail(&event->list, &head);
|
|
@@ -386,7 +448,7 @@ void hdmi_cec_handle(u16 cec_stat)
|
|
return;
|
|
}
|
|
for (i = 0; i < hdmi_cec_data.msg_len; i++)
|
|
- hdmi_writeb(hdmi_cec_data.last_msg[i], HDMI_CEC_TX_DATA0+i);
|
|
+ hdmi_writeb(hdmi_cec_data.last_msg[i], tx_reg[i]);
|
|
hdmi_writeb(hdmi_cec_data.msg_len, HDMI_CEC_TX_CNT);
|
|
val = hdmi_readb(HDMI_CEC_CTRL);
|
|
val |= 0x01;
|
|
@@ -528,7 +590,7 @@ static ssize_t hdmi_cec_write(struct file *file, const char __user *buf,
|
|
msg_len = count;
|
|
hdmi_writeb(msg_len, HDMI_CEC_TX_CNT);
|
|
for (i = 0; i < msg_len; i++)
|
|
- hdmi_writeb(msg[i], HDMI_CEC_TX_DATA0+i);
|
|
+ hdmi_writeb(msg[i], tx_reg[i]);
|
|
|
|
/* FIXME : wait for free line */
|
|
/* Enable Sending */
|
|
@@ -605,15 +667,17 @@ static long hdmi_cec_ioctl(struct file *filp, u_int cmd,
|
|
}
|
|
hdmi_cec_data.Logical_address = (u8)arg;
|
|
if (hdmi_cec_data.Logical_address <= 7) {
|
|
- val = 1 << hdmi_cec_data.Logical_address;
|
|
- hdmi_writeb(val, HDMI_CEC_ADDR_L);
|
|
- hdmi_writeb(0, HDMI_CEC_ADDR_H);
|
|
+ cec_l_addr_l = 1 << hdmi_cec_data.Logical_address;
|
|
+ cec_l_addr_h = 0;
|
|
} else if (hdmi_cec_data.Logical_address > 7 && hdmi_cec_data.Logical_address <= 15) {
|
|
- val = 1 << (hdmi_cec_data.Logical_address - 8);
|
|
- hdmi_writeb(val, HDMI_CEC_ADDR_H);
|
|
- hdmi_writeb(0, HDMI_CEC_ADDR_L);
|
|
- } else
|
|
+ cec_l_addr_l = 0;
|
|
+ cec_l_addr_h = 1 << (hdmi_cec_data.Logical_address - 8);
|
|
+ } else{
|
|
+ mutex_unlock(&hdmi_cec_data.lock);
|
|
ret = -EINVAL;
|
|
+ }
|
|
+ hdmi_writeb(cec_l_addr_l, HDMI_CEC_ADDR_L);
|
|
+ hdmi_writeb(cec_l_addr_h, HDMI_CEC_ADDR_H);
|
|
mutex_unlock(&hdmi_cec_data.lock);
|
|
break;
|
|
case HDMICEC_IOC_STARTDEVICE:
|
|
@@ -621,8 +685,6 @@ static long hdmi_cec_ioctl(struct file *filp, u_int cmd,
|
|
val &= ~HDMI_MC_CLKDIS_CECCLK_DISABLE;
|
|
hdmi_writeb(val, HDMI_MC_CLKDIS);
|
|
|
|
- hdmi_writeb(0x01, HDMI_MC_LOCKONCLOCK);
|
|
- val = hdmi_readb(HDMI_MC_LOCKONCLOCK);
|
|
hdmi_writeb(0x02, HDMI_CEC_CTRL);
|
|
/* enable CEC receive */
|
|
hdmi_writel(0x84, 0x1003c);
|
|
@@ -748,6 +810,7 @@ static int __init hdmi_cec_init(void)
|
|
hdmi_cec_data.tx_answer = CEC_TX_AVAIL;
|
|
INIT_DELAYED_WORK(&hdmi_cec_data.hdmi_cec_work, hdmi_cec_worker);
|
|
INIT_DELAYED_WORK(&hdmi_cec_data.hdmi_cec_resend, hdmi_cec_resender);
|
|
+ register_sunxi_hdmi_notifier(&sunxi_hdmi_nb);
|
|
printk(KERN_INFO "HDMI CEC initialized\n");
|
|
goto out;
|
|
|
|
@@ -762,6 +825,7 @@ static int __init hdmi_cec_init(void)
|
|
|
|
static void __exit hdmi_cec_exit(void)
|
|
{
|
|
+ unregister_sunxi_hdmi_notifier(&sunxi_hdmi_nb);
|
|
|
|
if (hdmi_cec_data.cec_irq > 0)
|
|
free_irq(hdmi_cec_data.cec_irq, &hdmi_cec_data);
|
|
diff --git a/drivers/video/sunxi/disp2/hdmi/aw/hdmi_core.c b/drivers/video/sunxi/disp2/hdmi/aw/hdmi_core.c
|
|
index 2f3820c..b7f5f83 100755
|
|
--- a/drivers/video/sunxi/disp2/hdmi/aw/hdmi_core.c
|
|
+++ b/drivers/video/sunxi/disp2/hdmi/aw/hdmi_core.c
|
|
@@ -1,4 +1,5 @@
|
|
#include "hdmi_core.h"
|
|
+#include "../drv_hdmi_i.h"
|
|
|
|
static __s32 hdmi_state = HDMI_State_Idle;
|
|
static __u32 video_on = 0;
|
|
@@ -142,6 +143,7 @@ __s32 hdmi_main_task_loop(void)
|
|
video_on = 0;
|
|
audio_on = 0;
|
|
Hdmi_hpd_event();
|
|
+ sunxi_hdmi_notifier_call_chain(hdmi_state);
|
|
}
|
|
|
|
if((times++) >= 10) {
|
|
@@ -164,6 +166,8 @@ __s32 hdmi_main_task_loop(void)
|
|
if(HPD) {
|
|
hdmi_state = HDMI_State_EDID_Parse;
|
|
__inf("plugin\n");
|
|
+ sunxi_hdmi_notifier_call_chain(hdmi_state);
|
|
+
|
|
} else {
|
|
return 0;
|
|
}
|
|
@@ -177,7 +181,7 @@ __s32 hdmi_main_task_loop(void)
|
|
Hdmi_hpd_event();
|
|
if(video_enable)
|
|
set_video_enable(true);
|
|
-
|
|
+ sunxi_hdmi_notifier_call_chain(hdmi_state);
|
|
case HDMI_State_HPD_Done:
|
|
//__inf("HDMI_State_HPD_Done\n");
|
|
if(video_on && hdcp_enable)
|
|
@@ -518,6 +522,6 @@ __s32 video_enter_lp(void)
|
|
__s32 video_exit_lp(void)
|
|
{
|
|
bsp_hdmi_init();
|
|
-
|
|
+ sunxi_hdmi_notifier_call_chain(0x05);
|
|
return 0;
|
|
}
|
|
diff --git a/drivers/video/sunxi/disp2/hdmi/aw/hdmi_edid.h b/drivers/video/sunxi/disp2/hdmi/aw/hdmi_edid.h
|
|
index 201f4f1..01743c4 100755
|
|
--- a/drivers/video/sunxi/disp2/hdmi/aw/hdmi_edid.h
|
|
+++ b/drivers/video/sunxi/disp2/hdmi/aw/hdmi_edid.h
|
|
@@ -1,25 +1,25 @@
|
|
-#ifndef __HDMI_EDID_H_
|
|
-#define __HDMI_EDID_H_
|
|
-
|
|
-#define Abort_Current_Operation 0
|
|
-#define Special_Offset_Address_Read 1
|
|
-#define Explicit_Offset_Address_Write 2
|
|
-#define Implicit_Offset_Address_Write 3
|
|
-#define Explicit_Offset_Address_Read 4
|
|
-#define Implicit_Offset_Address_Read 5
|
|
-#define Explicit_Offset_Address_E_DDC_Read 6
|
|
-#define Implicit_Offset_Address_E_DDC_Read 7
|
|
-
|
|
+#ifndef __HDMI_EDID_H_
|
|
+#define __HDMI_EDID_H_
|
|
+
|
|
+#define Abort_Current_Operation 0
|
|
+#define Special_Offset_Address_Read 1
|
|
+#define Explicit_Offset_Address_Write 2
|
|
+#define Implicit_Offset_Address_Write 3
|
|
+#define Explicit_Offset_Address_Read 4
|
|
+#define Implicit_Offset_Address_Read 5
|
|
+#define Explicit_Offset_Address_E_DDC_Read 6
|
|
+#define Implicit_Offset_Address_E_DDC_Read 7
|
|
+
|
|
|
|
extern __u32 cec_phy_addr;
|
|
-//extern __u8 EDID_Buf[1024];
|
|
-extern __u8 Device_Support_VIC[512];
|
|
-extern __s32 ParseEDID(void);
|
|
-//extern __s32 DDC_Read(char cmd,char pointer,char offset,int nbyte,char * pbuf);
|
|
-//extern void DDC_Init(void);
|
|
-//extern void send_ini_sequence(void);
|
|
-extern __u32 GetIsHdmi(void);
|
|
-extern __u32 GetIsYUV(void);
|
|
+//extern __u8 EDID_Buf[1024];
|
|
+extern __u8 Device_Support_VIC[512];
|
|
+extern __s32 ParseEDID(void);
|
|
+//extern __s32 DDC_Read(char cmd,char pointer,char offset,int nbyte,char * pbuf);
|
|
+//extern void DDC_Init(void);
|
|
+//extern void send_ini_sequence(void);
|
|
+extern __u32 GetIsHdmi(void);
|
|
+extern __u32 GetIsYUV(void);
|
|
extern __s32 GetEdidInfo(void);
|
|
-
|
|
+
|
|
#endif //__HDMI_EDID_H_
|
|
\ No newline at end of file
|
|
diff --git a/drivers/video/sunxi/disp2/hdmi/drv_hdmi.c b/drivers/video/sunxi/disp2/hdmi/drv_hdmi.c
|
|
index bfd1a3a..bd0a49e 100755
|
|
--- a/drivers/video/sunxi/disp2/hdmi/drv_hdmi.c
|
|
+++ b/drivers/video/sunxi/disp2/hdmi/drv_hdmi.c
|
|
@@ -32,6 +32,25 @@ static bool b_hdmi_suspend;
|
|
static bool b_hdmi_suspend_pre;
|
|
__s32 Hdmi_suspend(void);
|
|
__s32 Hdmi_resume(void);
|
|
+static BLOCKING_NOTIFIER_HEAD(sunxi_hdmi_notifier_list);
|
|
+
|
|
+int register_sunxi_hdmi_notifier(struct notifier_block *nb)
|
|
+{
|
|
+ return blocking_notifier_chain_register(&sunxi_hdmi_notifier_list, nb);
|
|
+}
|
|
+EXPORT_SYMBOL(register_sunxi_hdmi_notifier);
|
|
+
|
|
+int unregister_sunxi_hdmi_notifier(struct notifier_block *nb)
|
|
+{
|
|
+ return blocking_notifier_chain_unregister(&sunxi_hdmi_notifier_list, nb);
|
|
+}
|
|
+EXPORT_SYMBOL(unregister_sunxi_hdmi_notifier);
|
|
+
|
|
+int sunxi_hdmi_notifier_call_chain(unsigned long val)
|
|
+{
|
|
+ int ret = blocking_notifier_call_chain(&sunxi_hdmi_notifier_list, val, NULL);
|
|
+ return ret;
|
|
+}
|
|
|
|
void hdmi_delay_ms(__u32 t)
|
|
{
|
|
diff --git a/drivers/video/sunxi/disp2/hdmi/drv_hdmi_i.h b/drivers/video/sunxi/disp2/hdmi/drv_hdmi_i.h
|
|
index 23b8b0d..163fead 100755
|
|
--- a/drivers/video/sunxi/disp2/hdmi/drv_hdmi_i.h
|
|
+++ b/drivers/video/sunxi/disp2/hdmi/drv_hdmi_i.h
|
|
@@ -64,6 +64,9 @@ __s32 Hdmi_get_hdcp_enable(void);
|
|
__s32 Hdmi_get_video_timming_info(disp_video_timings **video_info);
|
|
int Hdmi_get_video_info_index(u32 mode_id);
|
|
__s32 Hdmi_get_input_csc(void);
|
|
+int register_sunxi_hdmi_notifier(struct notifier_block *nb);
|
|
+int unregister_sunxi_hdmi_notifier(struct notifier_block *nb);
|
|
+extern int sunxi_hdmi_notifier_call_chain(unsigned long val);
|
|
|
|
extern __s32 hdmi_i2c_add_driver(void);
|
|
extern __s32 hdmi_i2c_del_driver(void);
|