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92 lines
2.5 KiB
Diff
92 lines
2.5 KiB
Diff
From 59f5e9b9a802a177727017218dcf026dc390c37d Mon Sep 17 00:00:00 2001
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From: Vasily Khoruzhick <anarsoul@gmail.com>
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Date: Thu, 19 Dec 2019 09:28:23 -0800
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Subject: arm64: dts: allwinner: a64: Add thermal sensors and thermal zones
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A64 has 3 thermal sensors: 1 for CPU, 2 for GPU.
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Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
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Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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---
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arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 42 +++++++++++++++++++++++++++
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1 file changed, 42 insertions(+)
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(limited to 'arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi')
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diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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index ab42c0664b3e..9a89324d02db 100644
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--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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@@ -10,6 +10,7 @@
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#include <dt-bindings/reset/sun50i-a64-ccu.h>
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#include <dt-bindings/reset/sun8i-de2.h>
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#include <dt-bindings/reset/sun8i-r-ccu.h>
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+#include <dt-bindings/thermal/thermal.h>
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/ {
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interrupt-parent = <&gic>;
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@@ -172,6 +173,29 @@
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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+ thermal-zones {
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+ cpu_thermal: cpu0-thermal {
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+ /* milliseconds */
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+ polling-delay-passive = <0>;
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+ polling-delay = <0>;
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+ thermal-sensors = <&ths 0>;
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+ };
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+
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+ gpu0_thermal: gpu0-thermal {
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+ /* milliseconds */
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+ polling-delay-passive = <0>;
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+ polling-delay = <0>;
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+ thermal-sensors = <&ths 1>;
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+ };
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+
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+ gpu1_thermal: gpu1-thermal {
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+ /* milliseconds */
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+ polling-delay-passive = <0>;
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+ polling-delay = <0>;
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+ thermal-sensors = <&ths 2>;
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+ };
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+ };
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+
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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@@ -446,6 +470,12 @@
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sid: eeprom@1c14000 {
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compatible = "allwinner,sun50i-a64-sid";
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reg = <0x1c14000 0x400>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ ths_calibration: thermal-sensor-calibration@34 {
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+ reg = <0x34 0x8>;
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+ };
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};
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crypto: crypto@1c15000 {
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@@ -771,6 +801,18 @@
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status = "disabled";
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};
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+ ths: thermal-sensor@1c25000 {
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+ compatible = "allwinner,sun50i-a64-ths";
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+ reg = <0x01c25000 0x100>;
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+ clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
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+ clock-names = "bus", "mod";
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+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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+ resets = <&ccu RST_BUS_THS>;
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+ nvmem-cells = <&ths_calibration>;
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+ nvmem-cell-names = "calibration";
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+ #thermal-sensor-cells = <1>;
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+ };
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+
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uart0: serial@1c28000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28000 0x400>;
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--
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cgit 1.2-0.3.lf.el7
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