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54 lines
1.8 KiB
Diff
54 lines
1.8 KiB
Diff
This patch enables clk initialisation of rk3399 cpu in u-boot proper.
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Normally it should only be initialised in SPL as it is "time consuming".
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Doing so however leaves cpus clocked to low frequencies
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for Rockchip's DDR/loader/trust with mainline u-boot scenario
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which does not involve SPL phase.
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Signed-off-by: Piotr Szczepanik <piter75@gmail.com>
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diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
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index 865b80cc..fe546436 100644
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--- a/drivers/clk/rockchip/clk_rk3399.c
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+++ b/drivers/clk/rockchip/clk_rk3399.c
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@@ -47,12 +47,9 @@ struct pll_div {
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.fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
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.postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
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-#if defined(CONFIG_SPL_BUILD)
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static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
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static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2);
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-#else
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static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1);
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-#endif
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static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600 * MHz, 3, 1, 1);
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static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600 * MHz, 1, 2, 1);
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@@ -1071,7 +1068,6 @@ static struct clk_ops rk3399_clk_ops = {
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#endif
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};
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-#ifdef CONFIG_SPL_BUILD
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static void rkclk_init(struct rockchip_cru *cru)
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{
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u32 aclk_div;
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@@ -1149,11 +1145,9 @@ static void rkclk_init(struct rockchip_cru *cru)
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hclk_div << HCLK_PERILP1_DIV_CON_SHIFT |
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HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT);
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}
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-#endif
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static int rk3399_clk_probe(struct udevice *dev)
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{
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-#ifdef CONFIG_SPL_BUILD
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struct rk3399_clk_priv *priv = dev_get_priv(dev);
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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@@ -1162,7 +1156,6 @@ static int rk3399_clk_probe(struct udevice *dev)
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priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
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#endif
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rkclk_init(priv->cru);
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-#endif
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return 0;
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}
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