mirror of
https://github.com/Fishwaldo/build.git
synced 2025-03-24 07:41:53 +00:00
116 lines
3.2 KiB
Diff
116 lines
3.2 KiB
Diff
From 3adc15dbb8f2b91f8b447397fdbd55650d51c3f7 Mon Sep 17 00:00:00 2001
|
|
From: Jerome Brunet <jbrunet@baylibre.com>
|
|
Date: Tue, 24 Jan 2017 10:50:40 +0100
|
|
Subject: [PATCH 67/93] clk: gxbb: add mpll0 enable support
|
|
|
|
Unlike mpll1 and mpll2, mpll0 has an additional enable / disable bit in
|
|
HHI_MPLL_CNTL. Model this oddity by adding a gate at the output of the
|
|
actual pll.
|
|
|
|
To make this transparent to the clock consumer, the existing CLKID_MPLL0
|
|
id is given to the gate. The actual pll is transfered to CLKID_MPLL0_PLL.
|
|
|
|
Fixes: 738f66d3211d ("clk: gxbb: add AmLogic GXBB clk controller driver")
|
|
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
|
|
|
|
Conflicts:
|
|
drivers/clk/meson/gxbb.c
|
|
drivers/clk/meson/gxbb.h
|
|
---
|
|
drivers/clk/meson/gxbb.c | 27 ++++++++++++++++++++++++---
|
|
drivers/clk/meson/gxbb.h | 3 ++-
|
|
2 files changed, 26 insertions(+), 4 deletions(-)
|
|
|
|
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
|
|
index 1f31933..4379a62 100644
|
|
--- a/drivers/clk/meson/gxbb.c
|
|
+++ b/drivers/clk/meson/gxbb.c
|
|
@@ -452,7 +452,13 @@
|
|
},
|
|
};
|
|
|
|
-static struct meson_clk_mpll gxbb_mpll0 = {
|
|
+/*
|
|
+ * Unlike mpll1 and mpll2, mpll0 has an additional enable / disable bit. Let's
|
|
+ * model this using a clock gate. To make this oddity transparent to the clock
|
|
+ * consumer, let's give the CLKID_MPLL0 id to the gate and let the rate
|
|
+ * propagate to the pll itself.
|
|
+ */
|
|
+static struct meson_clk_mpll gxbb_mpll0_pll = {
|
|
.sdm = {
|
|
.reg_off = HHI_MPLL_CNTL7,
|
|
.shift = 0,
|
|
@@ -475,13 +481,26 @@
|
|
},
|
|
.lock = &clk_lock,
|
|
.hw.init = &(struct clk_init_data){
|
|
- .name = "mpll0",
|
|
+ .name = "mpll0_pll",
|
|
.ops = &meson_clk_mpll_ops,
|
|
.parent_names = (const char *[]){ "fixed_pll" },
|
|
.num_parents = 1,
|
|
},
|
|
};
|
|
|
|
+static struct clk_gate gxbb_mpll0 = {
|
|
+ .reg = (void *)HHI_MPLL_CNTL,
|
|
+ .bit_idx = 25,
|
|
+ .lock = &clk_lock,
|
|
+ .hw.init = &(struct clk_init_data){
|
|
+ .name = "mpll0",
|
|
+ .ops = &clk_gate_ops,
|
|
+ .parent_names = (const char *[]){ "mpll0_pll" },
|
|
+ .num_parents = 1,
|
|
+ .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),
|
|
+ },
|
|
+};
|
|
+
|
|
static struct meson_clk_mpll gxbb_mpll1 = {
|
|
.sdm = {
|
|
.reg_off = HHI_MPLL_CNTL8,
|
|
@@ -870,6 +889,7 @@
|
|
[CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
|
|
[CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
|
|
[CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
|
|
+ [CLKID_MPLL0_PLL] = &gxbb_mpll0_pll.hw,
|
|
[CLKID_MALI] = &gxbb_mali.hw,
|
|
/* This sentinel entry makes sure the table is large enough */
|
|
[NR_CLKS] = NULL, /* Sentinel */
|
|
@@ -887,7 +907,7 @@
|
|
};
|
|
|
|
static struct meson_clk_mpll *const gxbb_clk_mplls[] = {
|
|
- &gxbb_mpll0,
|
|
+ &gxbb_mpll0_pll,
|
|
&gxbb_mpll1,
|
|
&gxbb_mpll2,
|
|
};
|
|
@@ -977,6 +997,7 @@
|
|
&gxbb_emmc_c,
|
|
&gxbb_mali_0_en,
|
|
&gxbb_mali_1_en,
|
|
+ &gxbb_mpll0,
|
|
};
|
|
|
|
static struct clk_mux *gxbb_clk_muxes[] = {
|
|
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
|
|
index 15705d3..366b766 100644
|
|
--- a/drivers/clk/meson/gxbb.h
|
|
+++ b/drivers/clk/meson/gxbb.h
|
|
@@ -265,11 +265,12 @@
|
|
/* CLKID_SD_EMMC_A */
|
|
/* CLKID_SD_EMMC_B */
|
|
/* CLKID_SD_EMMC_C */
|
|
+#define CLKID_MPLL0_PLL 97
|
|
/* CLKID_MALI_0 */
|
|
/* CLKID_MALI_1 */
|
|
/* CLKID_MALI */
|
|
|
|
-#define NR_CLKS 100
|
|
+#define NR_CLKS 101
|
|
|
|
/* include the CLKIDs that have been made part of the stable DT binding */
|
|
#include <dt-bindings/clock/gxbb-clkc.h>
|
|
--
|
|
1.9.1
|
|
|