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f49c6f8e2b
1: update meson 4K support patches: 2, HDMI i2s improvement patches: 3, update vdec patches: 4, update meson audio patches: 5, add meson crypto engine driver 6, remove disabled patches: 7 remove unknown patch or no need 8, remove merged patches: 9, remove unknown patches from khadas should be covered by patches set 2 10, rename patches for better grouping 11, update kernel config accordingly Signed-off-by: Zhang Ning <832666+zhangn1985@users.noreply.github.com>
138 lines
5.2 KiB
Diff
138 lines
5.2 KiB
Diff
From 7602acfcd7cca5e3c8edb6b87801715a33e99944 Mon Sep 17 00:00:00 2001
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From: Maxime Jourdan <mjourdan@baylibre.com>
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Date: Wed, 5 Jun 2019 16:14:36 +0200
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Subject: [PATCH 14/14] media: meson: vdec: [WIP] HEVC IOMMU support
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Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com>
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---
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drivers/staging/media/meson/vdec/codec_hevc.c | 59 +++++++++++++------
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1 file changed, 41 insertions(+), 18 deletions(-)
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diff --git a/drivers/staging/media/meson/vdec/codec_hevc.c b/drivers/staging/media/meson/vdec/codec_hevc.c
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index 65d2ad4d8345..20bee7689dbd 100644
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--- a/drivers/staging/media/meson/vdec/codec_hevc.c
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+++ b/drivers/staging/media/meson/vdec/codec_hevc.c
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@@ -500,8 +500,11 @@ static void codec_hevc_output_frames(struct amvdec_session *sess)
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static int
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-codec_hevc_setup_workspace(struct amvdec_core *core, struct codec_hevc *hevc)
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+codec_hevc_setup_workspace(struct amvdec_session *sess,
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+ struct codec_hevc *hevc)
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{
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+ struct amvdec_core *core = sess->core;
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+ u32 revision = core->platform->revision;
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dma_addr_t wkaddr;
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/* Allocate some memory for the HEVC decoder's state */
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@@ -522,19 +525,32 @@ codec_hevc_setup_workspace(struct amvdec_core *core, struct codec_hevc *hevc)
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amvdec_write_dos(core, HEVC_PPS_BUFFER, wkaddr + PPS_OFFSET);
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amvdec_write_dos(core, HEVC_SAO_UP, wkaddr + SAO_UP_OFFSET);
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- if (core->platform->revision >= VDEC_REVISION_G12A)
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- amvdec_write_dos(core, HEVC_ASSIST_MMU_MAP_ADDR,
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- wkaddr + MMU_MAP_OFFSET);
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-
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- /* No MMU */
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- /*amvdec_write_dos(core, HEVC_STREAM_SWAP_BUFFER,
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- wkaddr + SWAP_BUF_OFFSET);
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- amvdec_write_dos(core, HEVC_STREAM_SWAP_BUFFER2,
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- wkaddr + SWAP_BUF2_OFFSET);*/
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+ if (codec_hevc_use_mmu(revision, sess->pixfmt_cap, hevc->is_10bit)) {
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+ amvdec_write_dos(core, HEVC_SAO_MMU_VH0_ADDR,
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+ wkaddr + MMU_VBH_OFFSET);
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+ amvdec_write_dos(core, HEVC_SAO_MMU_VH1_ADDR,
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+ wkaddr + MMU_VBH_OFFSET + (MMU_VBH_SIZE / 2));
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+
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+ if (revision >= VDEC_REVISION_G12A)
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+ amvdec_write_dos(core, HEVC_ASSIST_MMU_MAP_ADDR,
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+ hevc->common.mmu_map_paddr);
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+ else
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+ amvdec_write_dos(core, H265_MMU_MAP_BUFFER,
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+ hevc->common.mmu_map_paddr);
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+ } else if (revision < VDEC_REVISION_G12A) {
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+ amvdec_write_dos(core, HEVC_STREAM_SWAP_BUFFER,
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+ wkaddr + SWAP_BUF_OFFSET);
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+ amvdec_write_dos(core, HEVC_STREAM_SWAP_BUFFER2,
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+ wkaddr + SWAP_BUF2_OFFSET);
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+ }
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+
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amvdec_write_dos(core, HEVC_SCALELUT, wkaddr + SCALELUT_OFFSET);
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amvdec_write_dos(core, HEVC_DBLK_CFG4, wkaddr + DBLK_PARA_OFFSET);
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amvdec_write_dos(core, HEVC_DBLK_CFG5, wkaddr + DBLK_DATA_OFFSET);
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- amvdec_write_dos(core, HEVC_DBLK_CFGE, wkaddr + DBLK_DATA2_OFFSET);
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+ if (revision >= VDEC_REVISION_G12A)
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+ amvdec_write_dos(core, HEVC_DBLK_CFGE,
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+ wkaddr + DBLK_DATA2_OFFSET);
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+
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amvdec_write_dos(core, LMEM_DUMP_ADR, wkaddr + LMEM_OFFSET);
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return 0;
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@@ -555,7 +571,7 @@ static int codec_hevc_start(struct amvdec_session *sess)
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INIT_LIST_HEAD(&hevc->ref_frames_list);
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hevc->curr_poc = INVALID_POC;
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- ret = codec_hevc_setup_workspace(core, hevc);
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+ ret = codec_hevc_setup_workspace(sess, hevc);
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if (ret)
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goto free_hevc;
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@@ -720,6 +736,7 @@ codec_hevc_set_sao(struct amvdec_session *sess, struct hevc_frame *frame)
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{
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struct amvdec_core *core = sess->core;
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struct codec_hevc *hevc = sess->priv;
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+ struct vb2_buffer *vb = &frame->vbuf->vb2_buf;
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union rpm_param *param = &hevc->rpm_param;
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u32 pic_height_cu =
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(hevc->height + hevc->lcu_size - 1) / hevc->lcu_size;
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@@ -743,10 +760,10 @@ codec_hevc_set_sao(struct amvdec_session *sess, struct hevc_frame *frame)
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if (codec_hevc_use_downsample(sess->pixfmt_cap, hevc->is_10bit))
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buf_y_paddr =
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- hevc->common.fbc_buffer_paddr[frame->vbuf->vb2_buf.index];
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+ hevc->common.fbc_buffer_paddr[vb->index];
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else
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buf_y_paddr =
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- vb2_dma_contig_plane_dma_addr(&frame->vbuf->vb2_buf, 0);
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+ vb2_dma_contig_plane_dma_addr(vb, 0);
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if (codec_hevc_use_fbc(sess->pixfmt_cap, hevc->is_10bit)) {
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val = amvdec_read_dos(core, HEVC_SAO_CTRL5) & ~0xff0200;
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@@ -756,15 +773,23 @@ codec_hevc_set_sao(struct amvdec_session *sess, struct hevc_frame *frame)
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if (sess->pixfmt_cap == V4L2_PIX_FMT_NV12M) {
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buf_y_paddr =
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- vb2_dma_contig_plane_dma_addr(&frame->vbuf->vb2_buf, 0);
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+ vb2_dma_contig_plane_dma_addr(vb, 0);
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buf_u_v_paddr =
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- vb2_dma_contig_plane_dma_addr(&frame->vbuf->vb2_buf, 1);
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+ vb2_dma_contig_plane_dma_addr(vb, 1);
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amvdec_write_dos(core, HEVC_SAO_Y_START_ADDR, buf_y_paddr);
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amvdec_write_dos(core, HEVC_SAO_C_START_ADDR, buf_u_v_paddr);
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amvdec_write_dos(core, HEVC_SAO_Y_WPTR, buf_y_paddr);
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amvdec_write_dos(core, HEVC_SAO_C_WPTR, buf_u_v_paddr);
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}
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+ if (codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap,
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+ hevc->is_10bit)) {
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+ amvdec_write_dos(core, HEVC_CM_HEADER_START_ADDR,
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+ hevc->common.mmu_header_paddr[vb->index]);
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+ /* use HEVC_CM_HEADER_START_ADDR */
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+ amvdec_write_dos_bits(core, HEVC_SAO_CTRL5, BIT(10));
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+ }
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+
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amvdec_write_dos(core, HEVC_SAO_Y_LENGTH,
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amvdec_get_output_size(sess));
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amvdec_write_dos(core, HEVC_SAO_C_LENGTH,
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@@ -1351,8 +1376,6 @@ static irqreturn_t codec_hevc_threaded_isr(struct amvdec_session *sess)
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struct codec_hevc *hevc = sess->priv;
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u32 dec_status = amvdec_read_dos(core, HEVC_DEC_STATUS_REG);
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- printk("ISR!\n");
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-
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if (!hevc)
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return IRQ_HANDLED;
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--
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2.20.1
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