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69 lines
2.6 KiB
Diff
69 lines
2.6 KiB
Diff
From cd02f4b3e7ad491111dbd6e1eccf3db9bbc1bc81 Mon Sep 17 00:00:00 2001
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From: Neil Armstrong <narmstrong@baylibre.com>
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Date: Mon, 12 Nov 2018 16:08:13 +0100
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Subject: [PATCH] drm/meson: add HDMI div40 TMDS mode
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Add support for TMDS Clock > 3.4GHz for HDMI2.0 display modes.
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Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
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---
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drivers/gpu/drm/meson/meson_dw_hdmi.c | 24 ++++++++++++++++++++----
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1 file changed, 20 insertions(+), 4 deletions(-)
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diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c b/drivers/gpu/drm/meson/meson_dw_hdmi.c
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index d8c5cc3..118c49e 100644
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--- a/drivers/gpu/drm/meson/meson_dw_hdmi.c
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+++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c
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@@ -365,7 +365,8 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data,
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unsigned int wr_clk =
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readl_relaxed(priv->io_base + _REG(VPU_HDMI_SETTING));
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- DRM_DEBUG_DRIVER("%d:\"%s\"\n", mode->base.id, mode->name);
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+ DRM_DEBUG_DRIVER("%d:\"%s\" div%d\n", mode->base.id, mode->name,
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+ mode->clock > 340000 ? 40 : 10);
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/* Enable clocks */
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regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, 0xffff, 0x100);
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@@ -385,9 +386,17 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data,
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/* Enable normal output to PHY */
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dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_BIST_CNTL, BIT(12));
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- /* TMDS pattern setup (TOFIX pattern for 4k2k scrambling) */
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- dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01, 0x001f001f);
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- dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_23, 0x001f001f);
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+ /* TMDS pattern setup (TOFIX Handle the YUV420 case) */
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+ if (mode->clock > 340000) {
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+ dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01, 0);
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+ dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_23,
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+ 0x03ff03ff);
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+ } else {
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+ dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01,
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+ 0x001f001f);
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+ dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_23,
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+ 0x001f001f);
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+ }
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/* Load TMDS pattern */
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dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x1);
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@@ -413,6 +422,8 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data,
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/* Disable clock, fifo, fifo_wr */
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regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0);
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+ dw_hdmi_set_high_tmds_clock_ratio(hdmi);
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+
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msleep(100);
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/* Reset PHY 3 times in a row */
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@@ -562,6 +573,11 @@ dw_hdmi_mode_valid(struct drm_connector *connector,
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mode->vdisplay, mode->vsync_start,
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mode->vsync_end, mode->vtotal, mode->type, mode->flags);
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+ /* If sink max TMDS clock < 340MHz, we reject the HDMI2.0 modes */
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+ if (mode->clock > 340000 &&
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+ connector->display_info.max_tmds_clock < 340000)
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+ return MODE_BAD;
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+
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/* Check against non-VIC supported modes */
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if (!vic) {
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status = meson_venc_hdmi_supported_mode(mode);
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