mirror of
https://github.com/Fishwaldo/build.git
synced 2025-03-26 16:51:48 +00:00
162 lines
5.3 KiB
Text
162 lines
5.3 KiB
Text
diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi
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index e4a5857c1..9bbba9809 100644
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--- a/arch/arm/boot/dts/exynos5422-cpus.dtsi
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+++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi
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@@ -26,7 +26,7 @@
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compatible = "arm,cortex-a7";
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reg = <0x100>;
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clocks = <&clock CLK_KFC_CLK>;
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- clock-frequency = <1000000000>;
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+ clock-frequency = <1500000000>;
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cci-control-port = <&cci_control0>;
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operating-points-v2 = <&cluster_a7_opp_table>;
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#cooling-cells = <2>; /* min followed by max */
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@@ -38,7 +38,7 @@
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compatible = "arm,cortex-a7";
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reg = <0x101>;
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clocks = <&clock CLK_KFC_CLK>;
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- clock-frequency = <1000000000>;
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+ clock-frequency = <1500000000>;
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cci-control-port = <&cci_control0>;
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operating-points-v2 = <&cluster_a7_opp_table>;
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#cooling-cells = <2>; /* min followed by max */
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@@ -50,7 +50,7 @@
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compatible = "arm,cortex-a7";
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reg = <0x102>;
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clocks = <&clock CLK_KFC_CLK>;
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- clock-frequency = <1000000000>;
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+ clock-frequency = <1500000000>;
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cci-control-port = <&cci_control0>;
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operating-points-v2 = <&cluster_a7_opp_table>;
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#cooling-cells = <2>; /* min followed by max */
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@@ -62,7 +62,7 @@
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compatible = "arm,cortex-a7";
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reg = <0x103>;
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clocks = <&clock CLK_KFC_CLK>;
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- clock-frequency = <1000000000>;
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+ clock-frequency = <1500000000>;
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cci-control-port = <&cci_control0>;
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operating-points-v2 = <&cluster_a7_opp_table>;
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#cooling-cells = <2>; /* min followed by max */
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@@ -74,7 +74,7 @@
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compatible = "arm,cortex-a15";
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reg = <0x0>;
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clocks = <&clock CLK_ARM_CLK>;
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- clock-frequency = <1800000000>;
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+ clock-frequency = <2000000000>;
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cci-control-port = <&cci_control1>;
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operating-points-v2 = <&cluster_a15_opp_table>;
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#cooling-cells = <2>; /* min followed by max */
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@@ -86,7 +86,7 @@
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compatible = "arm,cortex-a15";
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reg = <0x1>;
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clocks = <&clock CLK_ARM_CLK>;
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- clock-frequency = <1800000000>;
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+ clock-frequency = <2000000000>;
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cci-control-port = <&cci_control1>;
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operating-points-v2 = <&cluster_a15_opp_table>;
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#cooling-cells = <2>; /* min followed by max */
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@@ -98,7 +98,7 @@
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compatible = "arm,cortex-a15";
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reg = <0x2>;
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clocks = <&clock CLK_ARM_CLK>;
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- clock-frequency = <1800000000>;
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+ clock-frequency = <2000000000>;
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cci-control-port = <&cci_control1>;
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operating-points-v2 = <&cluster_a15_opp_table>;
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#cooling-cells = <2>; /* min followed by max */
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@@ -110,7 +110,7 @@
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compatible = "arm,cortex-a15";
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reg = <0x3>;
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clocks = <&clock CLK_ARM_CLK>;
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- clock-frequency = <1800000000>;
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+ clock-frequency = <2000000000>;
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cci-control-port = <&cci_control1>;
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operating-points-v2 = <&cluster_a15_opp_table>;
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#cooling-cells = <2>; /* min followed by max */
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diff --git a/arch/arm/boot/dts/exynos5800.dtsi b/arch/arm/boot/dts/exynos5800.dtsi
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index 57d3b319f..5e6b55094 100644
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--- a/arch/arm/boot/dts/exynos5800.dtsi
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+++ b/arch/arm/boot/dts/exynos5800.dtsi
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@@ -21,6 +21,19 @@
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};
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&cluster_a15_opp_table {
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+ opp-2000000000 {
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+ opp-hz = /bits/ 64 <2000000000>;
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+ opp-microvolt = <1312500>;
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+ clock-latency-ns = <140000>;
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+ };
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+ opp-1900000000 {
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+ opp-hz = /bits/64 <1900000000>;
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+ opp-microvolt = <1250000>;
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+ clock-latency-ns = <140000>;
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+ };
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+ opp-1800000000 {
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+ opp-microvolt = <1200000>;
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+ };
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opp-1700000000 {
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opp-microvolt = <1250000>;
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};
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@@ -82,8 +95,20 @@
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};
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&cluster_a7_opp_table {
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+ opp-1500000000 {
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+ opp-hz = /bits/ 64 <1500000000>;
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+ opp-microvolt = <1250000>;
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+ clock-latency-ns = <140000>;
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+ };
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+ opp-1400000000 {
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+ opp-hz = /bits/ 64 <1400000000>;
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+ opp-microvolt = <1250000>;
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+ clock-latency-ns = <140000>;
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+ };
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opp-1300000000 {
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+ opp-hz = /bits/ 64 <1300000000>;
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opp-microvolt = <1250000>;
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+ clock-latency-ns = <140000>;
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};
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opp-1200000000 {
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opp-microvolt = <1250000>;
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diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
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index 95e1bf694..04f049832 100644
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--- a/drivers/clk/samsung/clk-exynos5420.c
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+++ b/drivers/clk/samsung/clk-exynos5420.c
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@@ -1398,6 +1398,8 @@ static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {
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((cpud) << 4)))
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static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst = {
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+ { 2000000, E5420_EGL_DIV0(3, 7, 7, 4), },
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+ { 1900000, E5420_EGL_DIV0(3, 7, 7, 4), },
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{ 1800000, E5420_EGL_DIV0(3, 7, 7, 4), },
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{ 1700000, E5420_EGL_DIV0(3, 7, 7, 3), },
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{ 1600000, E5420_EGL_DIV0(3, 7, 7, 3), },
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@@ -1445,6 +1447,7 @@ static const struct exynos_cpuclk_cfg_data exynos5800_eglclk_d[] __initconst = {
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((((kpll) << 24) | ((pclk) << 20) | ((aclk) << 4)))
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static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = {
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+ { 1500000, E5420_KFC_DIV(3, 5, 3), },
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{ 1400000, E5420_KFC_DIV(3, 5, 3), }, /* for Exynos5800 */
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{ 1300000, E5420_KFC_DIV(3, 5, 2), },
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{ 1200000, E5420_KFC_DIV(3, 5, 2), },
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diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c
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index f53fb41ef..04215e3c3 100644
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--- a/drivers/cpufreq/cpufreq.c
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+++ b/drivers/cpufreq/cpufreq.c
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@@ -1229,6 +1229,15 @@ static int cpufreq_online(unsigned int cpu)
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cpumask_and(policy->cpus, policy->cpus, cpu_online_mask);
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if (new_policy) {
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+
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+ if (cpumask_test_cpu(0, policy->cpus)) {
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+ policy->min = 200000;
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+ policy->max = 1500000;
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+ } else {
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+ policy->min = 200000;
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+ policy->max = 2000000;
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+ }
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+
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policy->user_policy.min = policy->min;
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policy->user_policy.max = policy->max;
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