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73 lines
2.2 KiB
Diff
73 lines
2.2 KiB
Diff
From 5afd98f6db25b34a96bfc7544681dbf40896c1fd Mon Sep 17 00:00:00 2001
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From: Icenowy Zheng <icenowy@aosc.io>
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Date: Sat, 23 Sep 2017 08:15:29 +0800
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Subject: [PATCH 035/146] clk: sunxi-ng: add mux and pll notifiers for A64 CPU
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clock
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The A64 PLL_CPU clock has the same instability if some factor changed
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without the PLL gated like other SoCs with sun6i-style CCU, e.g. A33,
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H3.
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Add the mux and pll notifiers for A64 CPU clock to workaround the
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problem.
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Fixes: c6a0637460c2 ("clk: sunxi-ng: Add A64 clocks")
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Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
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---
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drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 28 ++++++++++++++++++++++++++-
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1 file changed, 27 insertions(+), 1 deletion(-)
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diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
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index ee9c12cf3f08..1fe3c3fbc9bc 100644
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--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
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+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
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@@ -896,11 +896,26 @@ static const struct sunxi_ccu_desc sun50i_a64_ccu_desc = {
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.num_resets = ARRAY_SIZE(sun50i_a64_ccu_resets),
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};
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+static struct ccu_pll_nb sun50i_a64_pll_cpu_nb = {
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+ .common = &pll_cpux_clk.common,
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+ /* copy from pll_cpux_clk */
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+ .enable = BIT(31),
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+ .lock = BIT(28),
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+};
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+
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+static struct ccu_mux_nb sun50i_a64_cpu_nb = {
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+ .common = &cpux_clk.common,
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+ .cm = &cpux_clk.mux,
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+ .delay_us = 1, /* > 8 clock cycles at 24 MHz */
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+ .bypass_index = 1, /* index of 24 MHz oscillator */
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+};
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+
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static int sun50i_a64_ccu_probe(struct platform_device *pdev)
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{
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struct resource *res;
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void __iomem *reg;
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u32 val;
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+ int ret;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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reg = devm_ioremap_resource(&pdev->dev, res);
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@@ -914,7 +929,18 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev)
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writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
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- return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_a64_ccu_desc);
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+ ret = sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_a64_ccu_desc);
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+ if (ret)
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+ return ret;
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+
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+ /* Gate then ungate PLL CPU after any rate changes */
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+ ccu_pll_notifier_register(&sun50i_a64_pll_cpu_nb);
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+
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+ /* Reparent CPU during PLL CPU rate changes */
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+ ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
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+ &sun50i_a64_cpu_nb);
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+
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+ return 0;
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}
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static const struct of_device_id sun50i_a64_ccu_ids[] = {
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--
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2.17.1
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