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58 lines
2.3 KiB
Diff
58 lines
2.3 KiB
Diff
From 147f9cfda19a2b6af572b0f46cf99a2907081993 Mon Sep 17 00:00:00 2001
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From: Neil Armstrong <narmstrong@baylibre.com>
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Date: Wed, 14 Nov 2018 16:48:50 +0100
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Subject: [PATCH] drm/bridge: dw-hdmi: Add SCDC and TMDS Scrambling support
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Add support for SCDC Setup for TMDS Clock > 3.4GHz and enable TMDS
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Scrambling when supported or mandatory.
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This patch also adds an helper to setup the control bit to support
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the hight TMDS Bit Period/TMDS Clock-Period Ratio as required with
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TMDS Clock > 3.4GHz for HDMI2.0 3840x2160@60/50 modes.
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These changes were based on work done by Huicong Xu <xhc@rock-chips.com>
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and Nickey Yang <nickey.yang@rock-chips.com> to support HDMI2.0 modes
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on the Rockchip 4.4 BSP kernel at [1]
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[1] https://github.com/rockchip-linux/kernel/tree/release-4.4
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Cc: Nickey Yang <nickey.yang@rock-chips.com>
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Cc: Huicong Xu <xhc@rock-chips.com>
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Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
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---
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drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 45 +++++++++++++++++++++--
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drivers/gpu/drm/bridge/synopsys/dw-hdmi.h | 1 +
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include/drm/bridge/dw_hdmi.h | 1 +
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3 files changed, 44 insertions(+), 3 deletions(-)
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diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
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index 1fc12708dbb5..2a30d8393477 100644
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--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
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+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
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@@ -1573,6 +1592,26 @@ static void hdmi_av_composer(struct dw_hdmi *hdmi,
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vsync_len /= 2;
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}
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+ /* Scrambling Control */
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+ if (hdmi_info->scdc.supported) {
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+ if (vmode->mpixelclock > 340000000 ||
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+ hdmi_info->scdc.scrambling.low_rates) {
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+ drm_scdc_readb(&hdmi->i2c->adap, SCDC_SINK_VERSION,
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+ &bytes);
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+ drm_scdc_writeb(&hdmi->i2c->adap, SCDC_SOURCE_VERSION,
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+ bytes);
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+ drm_scdc_set_scrambling(&hdmi->i2c->adap, 1);
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+ hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
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+ HDMI_MC_SWRSTZ);
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+ hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL);
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+ } else {
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+ hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL);
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+ hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
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+ HDMI_MC_SWRSTZ);
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+ drm_scdc_set_scrambling(&hdmi->i2c->adap, 0);
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+ }
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+ }
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+
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/* Set up horizontal active pixel width */
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hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1);
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hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0);
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