build/patch/kernel/sun50i-dev/a64-DT-DVFS.patch

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index c8e7afa0..435e8f62 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -50,12 +50,72 @@
 #include <dt-bindings/reset/sun8i-de2.h>
 #include <dt-bindings/clock/sun8i-r-ccu.h>
 #include <dt-bindings/reset/sun8i-r-ccu.h>
+#include <dt-bindings/thermal/thermal.h>
 
 / {
 	interrupt-parent = <&gic>;
 	#address-cells = <1>;
 	#size-cells = <1>;
 
+	cpu0_opp_table: opp_table0 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp@408000000 {
+			opp-hz = /bits/ 64 <408000000>;
+			opp-microvolt = <1000000 1000000 1300000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+
+		opp@648000000 {
+			opp-hz = /bits/ 64 <648000000>;
+			opp-microvolt = <1040000 1040000 1300000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+
+		opp@816000000 {
+			opp-hz = /bits/ 64 <816000000>;
+			opp-microvolt = <1080000 1080000 1300000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+
+		opp@912000000 {
+		       opp-hz = /bits/ 64 <912000000>;
+		       opp-microvolt = <1120000 1120000 1300000>;
+		       clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+
+		opp@960000000 {
+		       opp-hz = /bits/ 64 <960000000>;
+		       opp-microvolt = <1160000 1160000 1300000>;
+		       clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+
+		opp@1008000000 {
+		       opp-hz = /bits/ 64 <1008000000>;
+		       opp-microvolt = <1200000 1200000 1300000>;
+		       clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+
+		opp@1056000000 {
+		       opp-hz = /bits/ 64 <1056000000>;
+		       opp-microvolt = <1240000 1240000 1300000>;
+		       clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+
+		opp@1104000000 {
+		       opp-hz = /bits/ 64 <1104000000>;
+		       opp-microvolt = <1260000 1260000 1300000>;
+		       clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+
+		opp@1152000000 {
+		       opp-hz = /bits/ 64 <1152000000>;
+		       opp-microvolt = <1300000 1300000 1300000>;
+		       clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -65,6 +125,12 @@
 			device_type = "cpu";
 			reg = <0>;
 			enable-method = "psci";
+			clocks = <&ccu 21>;
+			clock-names = "cpu";
+			operating-points-v2 = <&cpu0_opp_table>;
+			#cooling-cells = <2>;
+			cooling-min-level = <0>;
+			cooling-max-level = <8>;
 		};
 
 		cpu1: cpu@1 {
@@ -72,6 +138,7 @@
 			device_type = "cpu";
 			reg = <1>;
 			enable-method = "psci";
+			clocks = <&ccu 21>;
 		};
 
 		cpu2: cpu@2 {
@@ -79,6 +146,7 @@
 			device_type = "cpu";
 			reg = <2>;
 			enable-method = "psci";
+			clocks = <&ccu 21>;
 		};
 
 		cpu3: cpu@3 {
@@ -86,6 +154,58 @@
 			device_type = "cpu";
 			reg = <3>;
 			enable-method = "psci";
+			clocks = <&ccu 21>;
+		};
+	};
+
+	thermal-zones {
+		cpu_thermal: cpu_thermal {
+			polling-delay-passive = <330>;
+			polling-delay = <1000>;
+			thermal-sensors = <&scpi_cpu_thermal 0>;
+
+			trips {
+				cpu_warm: cpu_warm {
+					temperature = <65000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu_hot: cpu_hot {
+					temperature = <75000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu_very_hot: cpu_very_hot {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu_crit: cpu_crit {
+					temperature = <105000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+				cpu_warm_limit_cpu {
+					trip = <&cpu_warm>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT 2>;
+				};
+
+				cpu_hot_limit_cpu {
+					trip = <&cpu_hot>;
+					cooling-device = <&cpu0 3 5>;
+				};
+
+				cpu_very_hot_limit_cpu {
+					trip = <&cpu_very_hot>;
+					cooling-device = <&cpu0 6 THERMAL_NO_LIMIT>;
+				};
+			};
 		};
 	};
 
@@ -149,6 +269,37 @@
 			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 	};
 
+	mailbox: mbox@0 {
+		compatible = "arm,smc-mbox";
+		#mbox-cells = <1>;
+		arm,smc-func-ids = <0x82000001>;
+	};
+
+	sram: sram@10000{
+		compatible = "mmio-sram";
+		reg = <0x10000 0x8000>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x10000 0x8000>;
+
+		cpu_scp_mem: scp-shmem@7e00 {
+			compatible = "mmio-sram";
+			reg = <0x7e00 0x200>;
+		};
+	};
+
+	scpi {
+		compatible = "arm,scpi";
+		mboxes = <&mailbox 0>;
+		shmem = <&cpu_scp_mem>;
+
+		scpi_cpu_thermal: sensors {
+			compatible = "arm,scpi-sensors";
+			#thermal-sensor-cells = <1>;
+		};
+	};
+
 	soc {
 		compatible = "simple-bus";
 		#address-cells = <1>;
@@ -477,6 +628,8 @@
 			clock-names = "hosc", "losc";
 			#clock-cells = <1>;
 			#reset-cells = <1>;
+			assigned-clocks = <&ccu CLK_THS>;
+			assigned-clock-rates = <4000000>;
 		};
 
 		pio: pinctrl@1c20800 {