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AR-1 - Adding support category for distributions AR-4 - Remove Allwinner legacy AR-5 - Drop Udoo family and move Udoo board into newly created imx6 family AR-9 - Rename sunxi-next to sunxi-legacy AR-10 - Rename sunxi-dev to sunxi-current AR-11 - Adding Radxa Rockpi S support AR-13 - Rename rockchip64-default to rockchip64-legacy AR-14 - Add rockchip64-current as mainline source AR-15 - Drop Rockchip 4.19.y NEXT, current become 5.3.y AR-16 - Rename RK3399 default to legacy AR-17 - Rename Odroid XU4 next and default to legacy 4.14.y, add DEV 5.4.y AR-18 - Add Odroid N2 current mainline AR-19 - Move Odroid C1 to meson family AR-20 - Rename mvebu64-default to mvebu64-legacy AR-21 - Rename mvebu-default to mvebu-legacy AR-22 - Rename mvebu-next to mvebu-current AR-23 - Drop meson64 default and next, current becomes former DEV 5.3.y AR-24 - Drop cubox family and move Cubox/Hummingboard boards under imx6 AR-26 - Adjust motd AR-27 - Enabling distribution release status AR-28 - Added new GCC compilers AR-29 - Implementing Ubuntu Eoan AR-30 - Add desktop packages per board or family AR-31 - Remove (Ubuntu/Debian) distribution name from image filename AR-32 - Move arch configs from configuration.sh to separate arm64 and armhf config files AR-33 - Revision numbers for beta builds changed to day_in_the_year AR-34 - Patches support linked patches AR-35 - Break meson64 family into gxbb and gxl AR-36 - Add Nanopineo2 Black AR-38 - Upgrade option from old branches to new one via armbian-config AR-41 - Show full timezone info AR-43 - Merge Odroid N2 to meson64 AR-44 - Enable FORCE_BOOTSCRIPT_UPDATE for all builds
151 lines
5.3 KiB
Text
151 lines
5.3 KiB
Text
From 8477a566b36aaae77e53a9949f963ce6ebad55fe Mon Sep 17 00:00:00 2001
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From: Ondrej Jirman <megous@megous.com>
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Date: Thu, 12 Jan 2017 16:34:57 +0100
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Subject: [PATCH] clk: sunxi-ng: Set maximum M = 1 for H3 pll-cpux clock
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When using M factor greater than 1 system is experiencing
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occasional lockups.
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This change was verified to fix lockups with PLL stress
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tester available at https://github.com/megous/h3-firmware.
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Note that M factor must not be used outside the kernel
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either, so for example u-boot needs a similar patch.
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---
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drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 24 +++++++++++++++---------
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1 file changed, 15 insertions(+), 9 deletions(-)
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diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
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index 77ed0b0ba6819..8d47742def49d 100644
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--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
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+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
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@@ -30,15 +30,21 @@
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#include "ccu-sun8i-h3.h"
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-static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpux_clk, "pll-cpux",
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- "osc24M", 0x000,
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- 8, 5, /* N */
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- 4, 2, /* K */
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- 0, 2, /* M */
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- 16, 2, /* P */
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- BIT(31), /* gate */
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- BIT(28), /* lock */
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- CLK_SET_RATE_UNGATE);
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+static struct ccu_nkmp pll_cpux_clk = {
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+ .enable = BIT(31),
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+ .lock = BIT(28),
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+ .n = _SUNXI_CCU_MULT(8, 5),
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+ .k = _SUNXI_CCU_MULT(4, 2),
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+ .m = _SUNXI_CCU_DIV_MAX(0, 2, 1),
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+ .p = _SUNXI_CCU_DIV(16, 2),
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+ .common = {
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+ .reg = 0x000,
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+ .hw.init = CLK_HW_INIT("pll-cpux",
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+ "osc24M",
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+ &ccu_nkmp_ops,
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+ CLK_SET_RATE_UNGATE),
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+ },
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+};
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/*
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* The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
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From c313a0ac340bf1131d475527171764dc49901895 Mon Sep 17 00:00:00 2001
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From: Ondrej Jirman <megous@megous.com>
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Date: Wed, 5 Apr 2017 15:43:48 +0200
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Subject: [PATCH] clk: sunxi-ng: Limit pll_cpux P factor for rates > 288MHz on
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H3
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Datasheet for H3 mandates that CPUX PLL must not use postdivider
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(P factor must be 1) for clock rates above 288MHz.
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Signed-off-by: Ondrej Jirman <megous@megous.com>
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---
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drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
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index 8d47742def49d..7cc9467f373f2 100644
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--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
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+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
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@@ -37,6 +37,7 @@ static struct ccu_nkmp pll_cpux_clk = {
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.k = _SUNXI_CCU_MULT(4, 2),
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.m = _SUNXI_CCU_DIV_MAX(0, 2, 1),
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.p = _SUNXI_CCU_DIV(16, 2),
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+ .max_rate_for_p = 288000000,
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.common = {
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.reg = 0x000,
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.hw.init = CLK_HW_INIT("pll-cpux",
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From f07a20e4ce93e7e0f333f9f6e57f14fd4ab66abd Mon Sep 17 00:00:00 2001
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From: Ondrej Jirman <megous@megous.com>
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Date: Thu, 12 Jan 2017 16:37:24 +0100
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Subject: [PATCH] clk: sunxi-ng: Allow to limit the use of NKMP clock's P
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factor
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Some SoCs mandate the maximum clock rate for which the use
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of postdivider P factor is allowed. Allow to configure maximum
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clock rate.
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Signed-off-by: Ondrej Jirman <megous@megous.com>
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---
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drivers/clk/sunxi-ng/ccu_nkmp.c | 13 ++++++++-----
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drivers/clk/sunxi-ng/ccu_nkmp.h | 1 +
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2 files changed, 9 insertions(+), 5 deletions(-)
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diff --git a/drivers/clk/sunxi-ng/ccu_nkmp.c b/drivers/clk/sunxi-ng/ccu_nkmp.c
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index ebd9436d2c7cd..96dbc543b2cbc 100644
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--- a/drivers/clk/sunxi-ng/ccu_nkmp.c
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+++ b/drivers/clk/sunxi-ng/ccu_nkmp.c
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@@ -33,16 +33,19 @@ static unsigned long ccu_nkmp_calc_rate(unsigned long parent,
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}
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static void ccu_nkmp_find_best(unsigned long parent, unsigned long rate,
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- struct _ccu_nkmp *nkmp)
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+ struct _ccu_nkmp *nkmp, struct ccu_nkmp *_nkmp)
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{
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unsigned long best_rate = 0;
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unsigned long best_n = 0, best_k = 0, best_m = 0, best_p = 0;
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- unsigned long _n, _k, _m, _p;
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+ unsigned long _n, _k, _m, _p, _max_p;
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+
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+ _max_p = (_nkmp->max_rate_for_p == 0 || rate <= _nkmp->max_rate_for_p) ?
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+ nkmp->max_p : nkmp->min_p;
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for (_k = nkmp->min_k; _k <= nkmp->max_k; _k++) {
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for (_n = nkmp->min_n; _n <= nkmp->max_n; _n++) {
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for (_m = nkmp->min_m; _m <= nkmp->max_m; _m++) {
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- for (_p = nkmp->min_p; _p <= nkmp->max_p; _p <<= 1) {
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+ for (_p = nkmp->min_p; _p <= _max_p; _p <<= 1) {
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unsigned long tmp_rate;
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tmp_rate = ccu_nkmp_calc_rate(parent,
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@@ -146,7 +149,7 @@ static long ccu_nkmp_round_rate(struct clk_hw *hw, unsigned long rate,
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_nkmp.min_p = 1;
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_nkmp.max_p = nkmp->p.max ?: 1 << ((1 << nkmp->p.width) - 1);
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- ccu_nkmp_find_best(*parent_rate, rate, &_nkmp);
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+ ccu_nkmp_find_best(*parent_rate, rate, &_nkmp, nkmp);
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rate = ccu_nkmp_calc_rate(*parent_rate, _nkmp.n, _nkmp.k,
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_nkmp.m, _nkmp.p);
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@@ -177,7 +180,7 @@ static int ccu_nkmp_set_rate(struct clk_hw *hw, unsigned long rate,
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_nkmp.min_p = 1;
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_nkmp.max_p = nkmp->p.max ?: 1 << ((1 << nkmp->p.width) - 1);
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- ccu_nkmp_find_best(parent_rate, rate, &_nkmp);
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+ ccu_nkmp_find_best(parent_rate, rate, &_nkmp, nkmp);
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n_mask = GENMASK(nkmp->n.width + nkmp->n.shift - 1, nkmp->n.shift);
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k_mask = GENMASK(nkmp->k.width + nkmp->k.shift - 1, nkmp->k.shift);
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diff --git a/drivers/clk/sunxi-ng/ccu_nkmp.h b/drivers/clk/sunxi-ng/ccu_nkmp.h
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index 6940503e7fc46..bbea3e5ed6fba 100644
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--- a/drivers/clk/sunxi-ng/ccu_nkmp.h
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+++ b/drivers/clk/sunxi-ng/ccu_nkmp.h
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@@ -33,6 +33,7 @@ struct ccu_nkmp {
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struct ccu_mult_internal k;
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struct ccu_div_internal m;
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struct ccu_div_internal p;
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+ unsigned long max_rate_for_p;
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unsigned int fixed_post_div;
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