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https://github.com/Fishwaldo/build.git
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150ac0c2af
AR-1 - Adding support category for distributions AR-4 - Remove Allwinner legacy AR-5 - Drop Udoo family and move Udoo board into newly created imx6 family AR-9 - Rename sunxi-next to sunxi-legacy AR-10 - Rename sunxi-dev to sunxi-current AR-11 - Adding Radxa Rockpi S support AR-13 - Rename rockchip64-default to rockchip64-legacy AR-14 - Add rockchip64-current as mainline source AR-15 - Drop Rockchip 4.19.y NEXT, current become 5.3.y AR-16 - Rename RK3399 default to legacy AR-17 - Rename Odroid XU4 next and default to legacy 4.14.y, add DEV 5.4.y AR-18 - Add Odroid N2 current mainline AR-19 - Move Odroid C1 to meson family AR-20 - Rename mvebu64-default to mvebu64-legacy AR-21 - Rename mvebu-default to mvebu-legacy AR-22 - Rename mvebu-next to mvebu-current AR-23 - Drop meson64 default and next, current becomes former DEV 5.3.y AR-24 - Drop cubox family and move Cubox/Hummingboard boards under imx6 AR-26 - Adjust motd AR-27 - Enabling distribution release status AR-28 - Added new GCC compilers AR-29 - Implementing Ubuntu Eoan AR-30 - Add desktop packages per board or family AR-31 - Remove (Ubuntu/Debian) distribution name from image filename AR-32 - Move arch configs from configuration.sh to separate arm64 and armhf config files AR-33 - Revision numbers for beta builds changed to day_in_the_year AR-34 - Patches support linked patches AR-35 - Break meson64 family into gxbb and gxl AR-36 - Add Nanopineo2 Black AR-38 - Upgrade option from old branches to new one via armbian-config AR-41 - Show full timezone info AR-43 - Merge Odroid N2 to meson64 AR-44 - Enable FORCE_BOOTSCRIPT_UPDATE for all builds
94 lines
3.8 KiB
Diff
94 lines
3.8 KiB
Diff
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
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index ee8ca48b..d5e11b69 100644
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--- a/arch/arm/boot/dts/rk3288.dtsi
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+++ b/arch/arm/boot/dts/rk3288.dtsi
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@@ -1064,7 +1064,7 @@
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<&cru PCLK_PERI>;
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assigned-clock-rates = <594000000>,
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<1250000000>, <300000000>,
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- <150000000>, <75000000>,
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+ <0>, <75000000>,
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<300000000>, <150000000>,
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<75000000>;
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};
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@@ -1315,6 +1315,8 @@
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resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
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reset-names = "axi", "ahb", "dclk";
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iommus = <&vopb_mmu>;
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+ assigned-clocks = <&cru DCLK_VOP0>;
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+ assigned-clock-parents = <&cru PLL_NPLL>;
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status = "disabled";
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vopb_out: port {
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diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
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index 0a9f31f2..183114d8 100644
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--- a/drivers/clk/rockchip/clk-pll.c
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+++ b/drivers/clk/rockchip/clk-pll.c
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@@ -364,6 +364,17 @@ static const struct rockchip_pll_rate_table *rockchip_get_pll_settings(
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static long rockchip_pll_round_rate(struct clk_hw *hw,
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unsigned long drate, unsigned long *prate)
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{
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+ struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
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+ const struct rockchip_pll_rate_table *rate;
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+
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+ /* Get required rate settings from table */
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+ rate = rockchip_get_pll_settings(pll, drate);
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+ if (!rate) {
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+ pr_debug("%s: Invalid rate : %lu for pll clk %s\n", __func__,
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+ drate, __clk_get_name(hw->clk));
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+ return -EINVAL;
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+ }
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+
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return drate;
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}
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diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
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index ca6c2ad3..f748a292 100644
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--- a/drivers/clk/rockchip/clk-rk3288.c
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+++ b/drivers/clk/rockchip/clk-rk3288.c
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@@ -105,6 +105,27 @@ static struct rockchip_pll_rate_table rk3288_pll_rates[] = {
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{ /* sentinel */ },
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};
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+static struct rockchip_pll_rate_table rk3288_npll_rates[] = {
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+ RK3066_PLL_RATE_NB(594000000, 1, 99, 4, 32),
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+ RK3066_PLL_RATE_NB(585000000, 6, 585, 4, 32),
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+ RK3066_PLL_RATE_NB(432000000, 3, 216, 4, 32),
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+ RK3066_PLL_RATE_NB(426000000, 3, 213, 4, 32),
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+ RK3066_PLL_RATE_NB(400000000, 1, 100, 6, 32),
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+ RK3066_PLL_RATE_NB(342000000, 3, 171, 4, 32),
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+ RK3066_PLL_RATE_NB(297000000, 2, 198, 8, 16),
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+ RK3066_PLL_RATE_NB(270000000, 1, 135, 12, 32),
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+ RK3066_PLL_RATE_NB(260000000, 1, 130, 12, 32),
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+ RK3066_PLL_RATE_NB(148500000, 1, 99, 16, 32),
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+ RK3066_PLL_RATE(148352000, 13, 1125, 14),
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+ RK3066_PLL_RATE_NB(146250000, 6, 585, 16, 32),
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+ RK3066_PLL_RATE_NB(108000000, 1, 54, 12, 32),
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+ RK3066_PLL_RATE_NB(106500000, 4, 213, 12, 32),
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+ RK3066_PLL_RATE_NB(85500000, 4, 171, 12, 32),
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+ RK3066_PLL_RATE_NB(74250000, 4, 198, 16, 32),
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+ RK3066_PLL_RATE(74176000, 26, 1125, 14),
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+ { /* sentinel */ },
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+};
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+
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#define RK3288_DIV_ACLK_CORE_M0_MASK 0xf
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#define RK3288_DIV_ACLK_CORE_M0_SHIFT 0
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#define RK3288_DIV_ACLK_CORE_MP_MASK 0xf
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@@ -214,7 +235,7 @@ static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = {
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[gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12),
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RK3288_MODE_CON, 12, 8, 0, rk3288_pll_rates),
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[npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3288_PLL_CON(16),
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- RK3288_MODE_CON, 14, 9, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
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+ RK3288_MODE_CON, 14, 9, 0, rk3288_npll_rates),
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};
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static struct clk_div_table div_hclk_cpu_t[] = {
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@@ -429,7 +450,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
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RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
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RK3288_CLKGATE_CON(3), 4, GFLAGS),
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- COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, 0,
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+ COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
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RK3288_CLKSEL_CON(27), 0, 2, MFLAGS, 8, 8, DFLAGS,
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RK3288_CLKGATE_CON(3), 1, GFLAGS),
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COMPOSITE(DCLK_VOP1, "dclk_vop1", mux_pll_src_cpll_gpll_npll_p, 0,
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