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95 lines
3.3 KiB
Diff
95 lines
3.3 KiB
Diff
From 9878125eb4b4ffe64f39bb4db431f2a69dad418b Mon Sep 17 00:00:00 2001
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From: Jernej Skrabec <jernej.skrabec@siol.net>
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Date: Sun, 3 Sep 2017 11:52:11 +0200
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Subject: [PATCH] clk: sunxi-ng: Fix crash during boot
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Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
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---
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drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 18 +++++++++---------
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1 file changed, 9 insertions(+), 9 deletions(-)
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diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
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index 36224ba93f9da..864dac96733b2 100644
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--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
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+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
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@@ -37,7 +37,7 @@ static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpux_clk, "pll-cpux",
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16, 2, /* P */
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BIT(31), /* gate */
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BIT(28), /* lock */
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- 0);
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+ CLK_SET_RATE_UNGATE);
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/*
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* The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
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@@ -55,7 +55,7 @@ static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
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0, 5, /* M */
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BIT(31), /* gate */
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BIT(28), /* lock */
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- 0);
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+ CLK_SET_RATE_UNGATE);
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static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
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"osc24M", 0x0010,
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@@ -67,7 +67,7 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
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297000000, /* frac rate 1 */
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BIT(31), /* gate */
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BIT(28), /* lock */
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- 0);
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+ CLK_SET_RATE_UNGATE);
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static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
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"osc24M", 0x0018,
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@@ -79,7 +79,7 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
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297000000, /* frac rate 1 */
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BIT(31), /* gate */
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BIT(28), /* lock */
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- 0);
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+ CLK_SET_RATE_UNGATE);
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static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr",
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"osc24M", 0x020,
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@@ -88,7 +88,7 @@ static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr",
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0, 2, /* M */
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BIT(31), /* gate */
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BIT(28), /* lock */
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- 0);
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+ CLK_SET_RATE_UNGATE);
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static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph0_clk, "pll-periph0",
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"osc24M", 0x028,
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@@ -97,7 +97,7 @@ static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph0_clk, "pll-periph0",
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BIT(31), /* gate */
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BIT(28), /* lock */
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2, /* post-div */
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- 0);
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+ CLK_SET_RATE_UNGATE);
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static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
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"osc24M", 0x0038,
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@@ -109,7 +109,7 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
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297000000, /* frac rate 1 */
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BIT(31), /* gate */
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BIT(28), /* lock */
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- 0);
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+ CLK_SET_RATE_UNGATE);
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static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph1_clk, "pll-periph1",
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"osc24M", 0x044,
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@@ -118,7 +118,7 @@ static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph1_clk, "pll-periph1",
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BIT(31), /* gate */
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BIT(28), /* lock */
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2, /* post-div */
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- 0);
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+ CLK_SET_RATE_UNGATE);
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static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
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"osc24M", 0x0048,
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@@ -130,7 +130,7 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
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297000000, /* frac rate 1 */
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BIT(31), /* gate */
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BIT(28), /* lock */
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- 0);
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+ CLK_SET_RATE_UNGATE);
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static const char * const cpux_parents[] = { "osc32k", "osc24M",
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"pll-cpux" , "pll-cpux" };
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