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179 lines
4.7 KiB
Diff
179 lines
4.7 KiB
Diff
From 9ff1163fc60ee6a38202ab1f5692db1ea185bf71 Mon Sep 17 00:00:00 2001
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From: Myy <myy@miouyouyou.fr>
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Date: Tue, 17 Jan 2017 19:48:23 +0000
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Subject: [PATCH 1/2] arm: dts: Adding and enabling VPU services addresses for
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RK3288 MiQi
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In order to use the Rockchip VPU on RK3288 devices, it is necessary to
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add the addresses of these Video Processing Units and enable them.
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Signed-off-by: Myy <myy@miouyouyou.fr>
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---
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arch/arm/boot/dts/rk3288-miqi.dts | 36 ++++++++++++++++
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arch/arm/boot/dts/rk3288.dtsi | 89 ++++++++++++++++++++++++++++++++++++++-
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2 files changed, 123 insertions(+), 2 deletions(-)
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diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
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index 6b0ce11..287447e 100644
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--- a/arch/arm/boot/dts/rk3288-miqi.dts
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+++ b/arch/arm/boot/dts/rk3288-miqi.dts
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@@ -48,6 +48,34 @@
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model = "mqmaker MiQi";
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compatible = "mqmaker,miqi", "rockchip,rk3288";
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+ sound {
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+ compatible = "simple-audio-card";
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+ simple-audio-card,format = "i2s";
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+ simple-audio-card,name = "DW-HDMI";
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+ simple-audio-card,mclk-fs = <512>;
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+
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+ simple-audio-card,dai-link@0 { /* I2S - S/PDIF */
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+ format = "i2s";
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+ cpu {
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+ sound-dai = <&i2s>;
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+ };
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+ codec {
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+ sound-dai = <&hdmi>;
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+ };
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+ };
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+
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+ /*
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+ * If you want to support more cards,
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+ * you can add more dai-link node,
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+ * such as
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+ *
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+ * simple-audio-card,dai-link@1 {
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+ * ......
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+ * }
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+ */
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+
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+ };
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+
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chosen {
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stdout-path = "serial2:115200n8";
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};
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@@ -571,6 +599,14 @@
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status = "okay";
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};
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+&hevc_service {
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+ status = "okay";
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+};
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+
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+&vpu_service {
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+ status = "okay";
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+};
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+
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&wdt {
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status = "okay";
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};
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diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
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index 8be8714..c5e83d0 100644
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--- a/arch/arm/boot/dts/rk3288.dtsi
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+++ b/arch/arm/boot/dts/rk3288.dtsi
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@@ -99,8 +99,8 @@
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resets = <&cru SRST_CORE0>;
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operating-points = <
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/* KHz uV */
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- 1800000 1350000
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- 1704000 1350000
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+ 1800000 1350000
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+ 1704000 1350000
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1608000 1350000
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1512000 1300000
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1416000 1200000
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@@ -179,6 +179,91 @@
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};
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};
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+ vpu: video-codec@ff9a0000 {
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+ compatible = "rockchip,rk3288-vpu";
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+ reg = <0xff9a0000 0x800>;
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+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "vepu", "vdpu";
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+ clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
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+ clock-names = "aclk", "hclk";
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+ power-domains = <&power RK3288_PD_VIDEO>;
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+ iommus = <&vpu_mmu>;
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+ assigned-clocks = <&cru ACLK_VCODEC>;
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+ assigned-clock-rates = <400000000>;
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+ status = "disabled";
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+ };
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+
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+ vpu_service: vpu-service@ff9a0000 {
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+ compatible = "rockchip,vpu_service";
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+ reg = <0xff9a0000 0x800>;
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+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "irq_enc", "irq_dec";
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+ clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
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+ clock-names = "aclk_vcodec", "hclk_vcodec";
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+ power-domains = <&power RK3288_PD_VIDEO>;
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+ rockchip,grf = <&grf>;
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+ resets = <&cru SRST_VCODEC_AXI>, <&cru SRST_VCODEC_AHB>;
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+ reset-names = "video_a", "video_h";
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+ iommus = <&vpu_mmu>;
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+ iommu_enabled = <1>;
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+ dev_mode = <0>;
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+ status = "disabled";
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+ /* 0 means ion, 1 means drm */
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+ allocator = <1>;
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+ };
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+
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+ vpu_mmu: iommu@ff9a0800 {
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+ compatible = "rockchip,iommu";
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+ reg = <0xff9a0800 0x100>;
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+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "vpu_mmu";
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+ power-domains = <&power RK3288_PD_VIDEO>;
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+ #iommu-cells = <0>;
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+ };
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+
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+ hevc_service: hevc-service@ff9c0000 {
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+ compatible = "rockchip,hevc_service";
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+ reg = <0xff9c0000 0x400>;
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+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "irq_dec";
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+ clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
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+ <&cru SCLK_HEVC_CORE>,
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+ <&cru SCLK_HEVC_CABAC>;
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+ clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core",
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+ "clk_cabac";
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+ /*
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+ * The 4K hevc would also work well with 500/125/300/300,
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+ * no more err irq and reset request.
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+ */
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+ assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
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+ <&cru SCLK_HEVC_CORE>,
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+ <&cru SCLK_HEVC_CABAC>;
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+ assigned-clock-rates = <400000000>, <100000000>,
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+ <300000000>, <300000000>;
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+
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+ resets = <&cru SRST_HEVC>;
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+ reset-names = "video";
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+ power-domains = <&power RK3288_PD_HEVC>;
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+ rockchip,grf = <&grf>;
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+ dev_mode = <1>;
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+ iommus = <&hevc_mmu>;
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+ iommu_enabled = <1>;
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+ status = "disabled";
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+ /* 0 means ion, 1 means drm */
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+ allocator = <1>;
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+ };
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+
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+ hevc_mmu: iommu@ff9c0440 {
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+ compatible = "rockchip,iommu";
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+ reg = <0xff9c0440 0x40>, <0xff9c0480 0x40>;
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+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "hevc_mmu";
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+ power-domains = <&power RK3288_PD_HEVC>;
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+ #iommu-cells = <0>;
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+ };
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+
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gpu: mali@ffa30000 {
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compatible = "arm,malit764",
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"arm,malit76x",
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--
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2.10.2
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