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5d3820e09a
Add missing DTB files for all Clearfog branches Add parameter for loading Clearfog Base DTB
199 lines
5 KiB
Diff
199 lines
5 KiB
Diff
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
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index 04f1729..df7fade 100644
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--- a/arch/arm/boot/dts/Makefile
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+++ b/arch/arm/boot/dts/Makefile
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@@ -96,7 +96,8 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-38x-modular.dtb \
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armada-385-customer1.dtb \
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armada-382-customer2.dtb \
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armada-385-customer3.dtb \
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- armada-388-clearfog.dtb
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+ armada-388-clearfog.dtb \
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+ armada-388-clearfog-base.dtb
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dtb-$(CONFIG_ARCH_MXC) += \
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imx25-karo-tx25.dtb \
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imx25-pdk.dtb \
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diff --git a/arch/arm/boot/dts/armada-388-clearfog-base.dts b/arch/arm/boot/dts/armada-388-clearfog-base.dts
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new file mode 100644
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index 0000000..63046d4
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--- /dev/null
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+++ b/arch/arm/boot/dts/armada-388-clearfog-base.dts
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@@ -0,0 +1,179 @@
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+/*
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+ * Device Tree file for SolidRun's ClearFog-a1 board
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+ *
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+ * Rabeeh Khoury <rabeeh@solid-run.com>
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+ *
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+ * This file is dual-licensed: you can use it either under the terms
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+ * of the GPL or the X11 license, at your option. Note that this dual
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+ * licensing only applies to this file, and not this project as a
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+ * whole.
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+ *
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+ * a) This file is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License
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+ * version 2 as published by the Free Software Foundation.
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+ *
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+ * This file is distributed in the hope that it will be useful
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * Or, alternatively
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+ *
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+ * b) Permission is hereby granted, free of charge, to any person
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+ * obtaining a copy of this software and associated documentation
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+ * files (the "Software"), to deal in the Software without
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+ * restriction, including without limitation the rights to use
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+ * copy, modify, merge, publish, distribute, sublicense, and/or
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+ * sell copies of the Software, and to permit persons to whom the
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+ * Software is furnished to do so, subject to the following
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+ * conditions:
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+ *
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+ * The above copyright notice and this permission notice shall be
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+ * included in all copies or substantial portions of the Software.
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+ *
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+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
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+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
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+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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+ * OTHER DEALINGS IN THE SOFTWARE.
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+*/
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+
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+/dts-v1/;
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+#include <dt-bindings/gpio/gpio.h>
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+#include "armada-385-388.dtsi"
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+
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+/ {
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+ model = "SolidRun ClearFog a1 board";
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+ compatible = "marvell,a388-db-gp", "marvell,armada388", "marvell,armada38x";
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+
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+ chosen {
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+ bootargs = "console=ttyS0,115200 earlyprintk";
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+ };
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+
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+ memory {
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+ device_type = "memory";
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+ reg = <0x00000000 0x10000000>; /* 256 MB */
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+ };
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+
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+ soc {
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+ internal-regs {
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+ ethernet@70000 {
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+ status = "okay";
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+ phy = <&phy0>;
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+ phy-mode = "rgmii";
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+ };
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+
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+ ethernet@30000 {
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+ status = "okay";
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+ phy = <&phy1>;
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+ phy-mode = "sgmii";
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+ };
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+
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+ ethernet@34000 {
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+ status = "okay";
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+ phy = <&phy2>;
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+ phy-mode = "sgmii";
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+ };
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+
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+ i2c0: i2c@11000 {
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+ status = "okay";
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+ clock-frequency = <100000>;
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+ };
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+
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+ i2c1: i2c@11100 {
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+ status = "okay";
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+ clock-frequency = <100000>;
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+ };
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+
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+ mdio {
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+ phy0: ethernet-phy@0 {
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+ reg = <0>;
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+ };
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+ phy1: ethernet-phy@1 {
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+ reg = <999>;
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+ };
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+ phy2: ethernet-phy@2 {
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+ reg = <999>;
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+ };
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+ };
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+
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+ sata@a8000 {
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+ status = "okay";
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+ };
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+
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+ sata@e0000 {
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+ status = "okay";
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+ };
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+
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+ tdm@b0000 {
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+ pinctrl-0 = <&tdm_pins>;
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+ pinctrl-names = "default";
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+ pclk-freq-mhz = <8>;
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+ };
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+
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+ sdhci@d8000 {
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+ broken-cd;
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+ wp-inverted;
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+ bus-width = <4>;
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+ status = "okay";
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+ no-1-8-v;
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+ };
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+
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+ serial@12000 {
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+ status = "okay";
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+ };
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+
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+ serial@12100 {
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+ status = "okay";
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+ };
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+
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+ spi1: spi@10680 {
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+ pinctrl-0 = <&spi1_pins>;
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+ pinctrl-names = "default";
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+ status = "okay";
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+
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+ spi-flash@0 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ compatible = "w25q32";
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+ reg = <0>; /* Chip select 0 */
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+ spi-max-frequency = <3000000>;
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+ };
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+ slic@0 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ compatible = "mv_slic";
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+ reg = <1>; /* Chip select 1 */
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+ spi-max-frequency = <3000000>;
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+ spi-1byte-cs;
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+ spi-cpol;
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+ spi-cpha;
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+ };
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+ };
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+
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+ crypto@9D000 {
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+ status = "okay";
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+ };
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+ };
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+
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+ pcie-controller {
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+ status = "okay";
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+ /*
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+ * The two PCIe units are accessible through
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+ * standard PCIe slots on the board.
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+ */
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+ pcie@2,0 {
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+ /* Port 1, Lane 0 */
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+ status = "okay";
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+ };
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+ pcie@3,0 {
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+ /* Port 2, Lane 0 */
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+ status = "okay";
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+ };
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+
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+ };
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+ };
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+};
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