mirror of
https://github.com/Fishwaldo/build.git
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988 lines
24 KiB
Diff
988 lines
24 KiB
Diff
diff --git a/arch/arm/boot/dts/rk3288-miniarm.dts b/arch/arm/boot/dts/rk3288-miniarm.dts
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new file mode 100644
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index 0000000..348e9be
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--- /dev/null
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+++ b/arch/arm/boot/dts/rk3288-miniarm.dts
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@@ -0,0 +1,673 @@
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+/*
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+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
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+ *
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+ * This file is dual-licensed: you can use it either under the terms
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+ * of the GPL or the X11 license, at your option. Note that this dual
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+ * licensing only applies to this file, and not this project as a
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+ * whole.
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+ *
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+ * a) This file is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License as
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+ * published by the Free Software Foundation; either version 2 of the
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+ * License, or (at your option) any later version.
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+ *
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+ * This file is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * Or, alternatively,
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+ *
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+ * b) Permission is hereby granted, free of charge, to any person
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+ * obtaining a copy of this software and associated documentation
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+ * files (the "Software"), to deal in the Software without
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+ * restriction, including without limitation the rights to use,
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+ * copy, modify, merge, publish, distribute, sublicense, and/or
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+ * sell copies of the Software, and to permit persons to whom the
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+ * Software is furnished to do so, subject to the following
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+ * conditions:
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+ *
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+ * The above copyright notice and this permission notice shall be
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+ * included in all copies or substantial portions of the Software.
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+ *
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+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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+ * OTHER DEALINGS IN THE SOFTWARE.
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+ */
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+
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+/dts-v1/;
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+
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+#include "rk3288.dtsi"
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+#include <dt-bindings/input/input.h>
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+#include <dt-bindings/clock/rockchip,rk808.h>
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+
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+/ {
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+ model = "Rockchip RK3288 Tinker Board";
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+ compatible = "asus,rk3288-tinker", "rockchip,rk3288";
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+
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+ memory@0 {
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+ reg = <0x0 0x80000000>;
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+ device_type = "memory";
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+ };
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+
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+ wireless-bluetooth {
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+ compatible = "bluetooth-platdata";
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+ uart_rts_gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
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+ pinctrl-names = "default","rts_gpio";
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+ pinctrl-0 = <&uart0_rts>;
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+ pinctrl-1 = <&uart0_gpios>;
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+ BT,reset_gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
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+ BT,wake_gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>;
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+ BT,wake_host_irq = <&gpio4 31 GPIO_ACTIVE_HIGH>;
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+ status = "okay";
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+ };
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+
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+ wireless-wlan {
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+ compatible = "wlan-platdata";
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+ rockchip,grf = <&grf>;
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+ wifi_chip_type = "8723bs";
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+ sdio_vref = <1800>;
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+ WIFI,host_wake_irq = <&gpio4 30 GPIO_ACTIVE_HIGH>;
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+ status = "okay";
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+ };
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+
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+ ext_gmac: external-gmac-clock {
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+ compatible = "fixed-clock";
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+ #clock-cells = <0>;
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+ clock-frequency = <125000000>;
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+ clock-output-names = "ext_gmac";
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+ };
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+
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+ gpio-keys {
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+ compatible = "gpio-keys";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ autorepeat;
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+
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pwrbtn>;
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+
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+ button@0 {
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+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
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+ linux,code = <KEY_POWER>;
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+ label = "GPIO Key Power";
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+ linux,input-type = <1>;
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+ gpio-key,wakeup = <1>;
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+ debounce-interval = <100>;
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+ };
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+ };
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+
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+ gpio-leds {
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+ compatible = "gpio-leds";
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+
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+ pwr-led {
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+ gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;
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+ linux,default-trigger = "default-on";
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+ };
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+
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+ act-led {
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+ gpios=<&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>;
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+ linux,default-trigger="mmc0";
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+ };
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+
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+
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+ heartbeat-led {
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+ gpios=<&gpio1 RK_PD1 GPIO_ACTIVE_HIGH>;
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+ linux,default-trigger="heartbeat";
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+ };
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+ };
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+
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+ sound {
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+ compatible = "simple-audio-card";
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+ simple-audio-card,format = "i2s";
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+ simple-audio-card,name = "rockchip,tinker-codec";
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+ simple-audio-card,mclk-fs = <512>;
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+ simple-audio-card,cpu {
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+ sound-dai = <&i2s>;
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+ };
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+ simple-audio-card,codec {
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+ sound-dai = <&hdmi>;
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+ };
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+ };
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+
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+ vcc_sys: vsys-regulator {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc_sys";
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+ regulator-min-microvolt = <5000000>;
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+ regulator-max-microvolt = <5000000>;
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+ regulator-always-on;
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+ regulator-boot-on;
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+ };
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+
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+ vcc_sd: sdmmc-regulator {
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+ compatible = "regulator-fixed";
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+ gpio = <&gpio7 11 GPIO_ACTIVE_LOW>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&sdmmc_pwr>;
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+ regulator-name = "vcc_sd";
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ startup-delay-us = <100000>;
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+ vin-supply = <&vcc_io>;
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+ };
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+
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+ sdio_pwrseq: sdio-pwrseq {
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+ compatible = "mmc-pwrseq-simple";
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+ clocks = <&rk808 RK808_CLKOUT1>;
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+ clock-names = "ext_clock";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&chip_enable_h>, <&wifi_enable_h>;
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+
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+ /*
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+ * On the module itself this is one of these (depending
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+ * on the actual card populated):
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+ * - SDIO_RESET_L_WL_REG_ON
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+ * - PDN (power down when low)
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+ */
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+ reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>, <&gpio4 RK_PD3 GPIO_ACTIVE_LOW>;
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+ };
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+
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+};
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+
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+&cpu0 {
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+ cpu0-supply = <&vdd_cpu>;
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+};
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+
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+&gmac {
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+ phy-supply = <&vcc33_lan>;
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+ phy-mode = "rgmii";
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+ clock_in_out = "input";
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+ snps,reset-gpio = <&gpio4 7 0>;
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+ snps,reset-active-low;
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+ snps,reset-delays-us = <0 10000 1000000>;
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+ assigned-clocks = <&cru SCLK_MAC>;
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+ assigned-clock-parents = <&ext_gmac>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&rgmii_pins>;
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+ tx_delay = <0x30>;
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+ rx_delay = <0x10>;
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+ status = "ok";
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+};
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+
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+&hdmi {
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+ ddc-i2c-bus = <&i2c5>;
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+ status = "okay";
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+};
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+
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+&i2c0 {
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+ status = "okay";
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+ clock-frequency = <400000>;
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+
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+ rk808: pmic@1b {
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+ compatible = "rockchip,rk808";
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+ reg = <0x1b>;
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+ interrupt-parent = <&gpio0>;
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+ interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pmic_int &global_pwroff &dvs_1 &dvs_2>;
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+ dvs-gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>,
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+ <&gpio0 12 GPIO_ACTIVE_HIGH>;
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+
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+ rockchip,system-power-controller;
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+ wakeup-source;
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+ #clock-cells = <1>;
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+ clock-output-names = "xin32k", "rk808-clkout2";
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+
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+ vcc1-supply = <&vcc_sys>;
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+ vcc2-supply = <&vcc_sys>;
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+ vcc3-supply = <&vcc_sys>;
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+ vcc4-supply = <&vcc_sys>;
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+ vcc6-supply = <&vcc_sys>;
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+ vcc7-supply = <&vcc_sys>;
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+ vcc8-supply = <&vcc_io>;
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+ vcc9-supply = <&vcc_io>;
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+ vcc10-supply = <&vcc_io>;
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+ vcc11-supply = <&vcc_sys>;
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+ vcc12-supply = <&vcc_io>;
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+ vddio-supply = <&vcc_io>;
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+
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+ regulators {
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+ vdd_cpu: DCDC_REG1 {
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <750000>;
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+ regulator-max-microvolt = <1450000>;
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+ regulator-name = "vdd_arm";
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+ regulator-ramp-delay = <6000>;
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+ regulator-state-mem {
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+ regulator-off-in-suspend;
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+ };
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+ };
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+
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+ vdd_gpu: DCDC_REG2 {
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <850000>;
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+ regulator-max-microvolt = <1250000>;
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+ regulator-name = "vdd_gpu";
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+ regulator-ramp-delay = <6000>;
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+ regulator-state-mem {
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+ regulator-on-in-suspend;
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+ regulator-suspend-microvolt = <1000000>;
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+ };
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+ };
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+
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+ vcc_ddr: DCDC_REG3 {
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-name = "vcc_ddr";
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+ regulator-state-mem {
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+ regulator-on-in-suspend;
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+ };
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+ };
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+
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+ vcc_io: DCDC_REG4 {
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-name = "vcc_io";
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+ regulator-state-mem {
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+ regulator-on-in-suspend;
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+ regulator-suspend-microvolt = <3300000>;
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+ };
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+ };
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+
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+ vcc18_ldo1: LDO_REG1 {
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <1800000>;
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+ regulator-name = "vcc18_ldo1";
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+ regulator-state-mem {
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+ regulator-on-in-suspend;
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+ regulator-suspend-microvolt = <1800000>;
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+ };
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+ };
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+
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+ vcc33_mipi: LDO_REG2 {
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-name = "vcc33_mipi";
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+ regulator-state-mem {
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+ regulator-off-in-suspend;
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+ };
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+ };
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+
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+ vdd_10: LDO_REG3 {
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <1000000>;
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+ regulator-max-microvolt = <1000000>;
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+ regulator-name = "vdd_10";
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+ regulator-state-mem {
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+ regulator-on-in-suspend;
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+ regulator-suspend-microvolt = <1000000>;
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+ };
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+ };
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+
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+ vcc18_codec: LDO_REG4 {
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <1800000>;
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+ regulator-name = "vcc18_codec";
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+ regulator-state-mem {
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+ regulator-on-in-suspend;
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+ regulator-suspend-microvolt = <1800000>;
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+ };
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+ };
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+
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+ vccio_sd: LDO_REG5 {
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-name = "vccio_sd";
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+ regulator-state-mem {
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+ regulator-on-in-suspend;
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+ regulator-suspend-microvolt = <3300000>;
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+ };
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+ };
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+
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+ vdd10_lcd: LDO_REG6 {
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <1000000>;
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+ regulator-max-microvolt = <1000000>;
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+ regulator-name = "vdd10_lcd";
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+ regulator-state-mem {
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+ regulator-on-in-suspend;
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+ regulator-suspend-microvolt = <1000000>;
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+ };
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+ };
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+
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+ vcc_18: LDO_REG7 {
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <1800000>;
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+ regulator-name = "vcc_18";
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+ regulator-state-mem {
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+ regulator-on-in-suspend;
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+ regulator-suspend-microvolt = <1800000>;
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+ };
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+ };
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+
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+ vcc18_lcd: LDO_REG8 {
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <1800000>;
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+ regulator-name = "vcc18_lcd";
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+ regulator-state-mem {
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+ regulator-on-in-suspend;
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+ regulator-suspend-microvolt = <1800000>;
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+ };
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+ };
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+
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+ vcc33_sd: SWITCH_REG1 {
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+ regulator-boot-on;
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+ regulator-name = "vcc33_sd";
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+ regulator-state-mem {
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+ regulator-on-in-suspend;
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+ };
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+ };
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+
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+ vcc33_lan: SWITCH_REG2 {
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-name = "vcc33_lan";
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+ regulator-state-mem {
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+ regulator-on-in-suspend;
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+ };
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+ };
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+ };
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+ };
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+};
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+
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+&i2c1 {
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+ status = "okay";
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+};
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+
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+&i2c2 {
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+ status = "okay";
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+
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+ eeprom:m24c08@50 {
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+ compatible = "at,24c08";
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+ reg = <0x50>;
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+ };
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+};
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+
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+&i2c3 {
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+ status = "okay";
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+};
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+
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+&i2c4 {
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+ status = "okay";
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+};
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+
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+&i2c5 {
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+ status = "okay";
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+};
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+
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+ &spi2 {
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+ status = "okay";
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+ max-freq = <50000000>;
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+ spidev@0 {
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+ compatible = "rockchip,spi_tinker";
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+ reg = <0>;
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+ spi-max-frequency = <50000000>;
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+ spi-cpha = <1>;
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+ //spi-cpol = <1>;
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+ };
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+ spidev@1 {
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+ compatible = "rockchip,spi_tinker";
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+ reg = <1>;
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+ spi-max-frequency = <50000000>;
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+ spi-cpha = <1>;
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+ //spi-cpol = <1>;
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+ };
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+ };
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+
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+&i2s {
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+ #sound-dai-cells = <0>;
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+ status = "okay";
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+};
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+
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+&sdio0 {
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+ status = "okay";
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+ clock-frequency = <50000000>;
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+ clock-freq-min-max = <200000 50000000>;
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+ bus-width = <4>;
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+ cap-sd-highspeed;
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+ cap-sdio-irq;
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+ disable-wp;
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+ keep-power-in-suspend;
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+ mmc-pwrseq = <&sdio_pwrseq>;
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+ non-removable;
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+ num-slots = <1>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
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+ sd-uhs-sdr104;
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+ supports-sdio;
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+
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+};
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+
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+
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+&io_domains {
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+ status = "okay";
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+ rockchip,grf = <&grf>;
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+ wifi-supply = <&vcc_18>;
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+ sdcard-supply = <&vccio_sd>;
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+};
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+
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+&pinctrl {
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+ pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
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+ drive-strength = <8>;
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+ };
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+
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+ pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
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+ bias-pull-up;
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+ drive-strength = <8>;
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+ };
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+
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+ backlight {
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+ bl_en: bl-en {
|
|
+ rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ buttons {
|
|
+ pwrbtn: pwrbtn {
|
|
+ rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ eth_phy {
|
|
+ eth_phy_pwr: eth-phy-pwr {
|
|
+ rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pmic {
|
|
+ pmic_int: pmic-int {
|
|
+ rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO \
|
|
+ &pcfg_pull_up>;
|
|
+ };
|
|
+
|
|
+ dvs_1: dvs-1 {
|
|
+ rockchip,pins = <RK_GPIO0 11 RK_FUNC_GPIO \
|
|
+ &pcfg_pull_down>;
|
|
+ };
|
|
+
|
|
+ dvs_2: dvs-2 {
|
|
+ rockchip,pins = <RK_GPIO0 12 RK_FUNC_GPIO \
|
|
+ &pcfg_pull_down>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sdio-pwrseq {
|
|
+ wifi_enable_h: wifienable-h {
|
|
+ rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+
|
|
+ chip_enable_h: chip-enable-h {
|
|
+ rockchip,pins = <4 27 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+
|
|
+ sdmmc {
|
|
+ sdmmc_bus4: sdmmc-bus4 {
|
|
+ rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
|
|
+ <6 17 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
|
|
+ <6 18 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
|
|
+ <6 19 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
|
|
+ };
|
|
+
|
|
+ sdmmc_clk: sdmmc-clk {
|
|
+ rockchip,pins = <6 20 RK_FUNC_1 \
|
|
+ &pcfg_pull_none_drv_8ma>;
|
|
+ };
|
|
+
|
|
+ sdmmc_cmd: sdmmc-cmd {
|
|
+ rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
|
|
+ };
|
|
+
|
|
+ sdmmc_pwr: sdmmc-pwr {
|
|
+ rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ usb {
|
|
+ host_vbus_drv: host-vbus-drv {
|
|
+ rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+
|
|
+ pwr_3g: pwr-3g {
|
|
+ rockchip,pins = <7 8 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ wireless-bluetooth {
|
|
+ uart0_gpios: uart0-gpios {
|
|
+ rockchip,pins = <4 19 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+};
|
|
+
|
|
+&pwm0 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&saradc {
|
|
+ vref-supply = <&vcc18_ldo1>;
|
|
+ status ="okay";
|
|
+};
|
|
+
|
|
+&sdmmc {
|
|
+ bus-width = <4>;
|
|
+ cap-mmc-highspeed;
|
|
+ cap-sd-highspeed;
|
|
+ sd-uhs-sdr12;
|
|
+ sd-uhs-sdr25;
|
|
+ sd-uhs-sdr50;
|
|
+ sd-uhs-sdr104;
|
|
+ card-detect-delay = <200>;
|
|
+ disable-wp; /* wp not hooked up */
|
|
+ num-slots = <1>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
|
|
+ status = "okay";
|
|
+ supports-sd;
|
|
+ vmmc-supply = <&vcc33_sd>;
|
|
+ vqmmc-supply = <&vccio_sd>;
|
|
+};
|
|
+
|
|
+&tsadc {
|
|
+ rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
|
|
+ rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&uart0 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&uart0_xfer>, <&uart0_cts>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&uart1 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&uart2 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&uart3 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&uart4 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usbphy {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usb_host0_ehci {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usb_host1 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usb_otg {
|
|
+ status= "okay";
|
|
+};
|
|
+
|
|
+&vopb {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&vopb_mmu {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&vopl {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&vopl_mmu {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&wdt {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+/* Support for Mali and Video codecs services */
|
|
+&gpu {
|
|
+ mali-supply = <&vdd_gpu>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&hevc_service {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&vpu_service {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
|
|
index 5d63ee0..458d545 100644
|
|
--- a/arch/arm/boot/dts/rk3288.dtsi
|
|
+++ b/arch/arm/boot/dts/rk3288.dtsi
|
|
@@ -43,7 +43,6 @@
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
#include <dt-bindings/pinctrl/rockchip.h>
|
|
#include <dt-bindings/clock/rk3288-cru.h>
|
|
-#include <dt-bindings/power/rk3288-power.h>
|
|
#include <dt-bindings/thermal/thermal.h>
|
|
#include <dt-bindings/power/rk3288-power.h>
|
|
#include <dt-bindings/soc/rockchip,boot-mode.h>
|
|
@@ -100,6 +99,8 @@
|
|
resets = <&cru SRST_CORE0>;
|
|
operating-points = <
|
|
/* KHz uV */
|
|
+ 1800000 1350000
|
|
+ 1704000 1350000
|
|
1608000 1350000
|
|
1512000 1300000
|
|
1416000 1200000
|
|
@@ -178,6 +179,129 @@
|
|
};
|
|
};
|
|
|
|
+ vpu: video-codec@ff9a0000 {
|
|
+ compatible = "rockchip,rk3288-vpu";
|
|
+ reg = <0xff9a0000 0x800>;
|
|
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "vepu", "vdpu";
|
|
+ clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
|
|
+ clock-names = "aclk", "hclk";
|
|
+ power-domains = <&power RK3288_PD_VIDEO>;
|
|
+ iommus = <&vpu_mmu>;
|
|
+ assigned-clocks = <&cru ACLK_VCODEC>;
|
|
+ assigned-clock-rates = <400000000>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ vpu_service: vpu-service@ff9a0000 {
|
|
+ compatible = "rockchip,vpu_service";
|
|
+ reg = <0xff9a0000 0x800>;
|
|
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "irq_enc", "irq_dec";
|
|
+ clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
|
|
+ clock-names = "aclk_vcodec", "hclk_vcodec";
|
|
+ power-domains = <&power RK3288_PD_VIDEO>;
|
|
+ rockchip,grf = <&grf>;
|
|
+ resets = <&cru SRST_VCODEC_AXI>, <&cru SRST_VCODEC_AHB>;
|
|
+ reset-names = "video_a", "video_h";
|
|
+ iommus = <&vpu_mmu>;
|
|
+ iommu_enabled = <1>;
|
|
+ dev_mode = <0>;
|
|
+ status = "disabled";
|
|
+ /* 0 means ion, 1 means drm */
|
|
+ allocator = <1>;
|
|
+ };
|
|
+
|
|
+ vpu_mmu: iommu@ff9a0800 {
|
|
+ compatible = "rockchip,iommu";
|
|
+ reg = <0xff9a0800 0x100>;
|
|
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "vpu_mmu";
|
|
+ power-domains = <&power RK3288_PD_VIDEO>;
|
|
+ #iommu-cells = <0>;
|
|
+ };
|
|
+
|
|
+ hevc_service: hevc-service@ff9c0000 {
|
|
+ compatible = "rockchip,hevc_service";
|
|
+ reg = <0xff9c0000 0x400>;
|
|
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "irq_dec";
|
|
+ clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
|
|
+ <&cru SCLK_HEVC_CORE>,
|
|
+ <&cru SCLK_HEVC_CABAC>;
|
|
+ clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core",
|
|
+ "clk_cabac";
|
|
+ /*
|
|
+ * The 4K hevc would also work well with 500/125/300/300,
|
|
+ * no more err irq and reset request.
|
|
+ */
|
|
+ assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
|
|
+ <&cru SCLK_HEVC_CORE>,
|
|
+ <&cru SCLK_HEVC_CABAC>;
|
|
+ assigned-clock-rates = <400000000>, <100000000>,
|
|
+ <300000000>, <300000000>;
|
|
+
|
|
+ resets = <&cru SRST_HEVC>;
|
|
+ reset-names = "video";
|
|
+ power-domains = <&power RK3288_PD_HEVC>;
|
|
+ rockchip,grf = <&grf>;
|
|
+ dev_mode = <1>;
|
|
+ iommus = <&hevc_mmu>;
|
|
+ iommu_enabled = <1>;
|
|
+ status = "disabled";
|
|
+ /* 0 means ion, 1 means drm */
|
|
+ allocator = <1>;
|
|
+ };
|
|
+
|
|
+ hevc_mmu: iommu@ff9c0440 {
|
|
+ compatible = "rockchip,iommu";
|
|
+ reg = <0xff9c0440 0x40>, <0xff9c0480 0x40>;
|
|
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "hevc_mmu";
|
|
+ power-domains = <&power RK3288_PD_HEVC>;
|
|
+ #iommu-cells = <0>;
|
|
+ };
|
|
+
|
|
+ gpu: mali@ffa30000 {
|
|
+ compatible = "arm,malit764",
|
|
+ "arm,malit76x",
|
|
+ "arm,malit7xx",
|
|
+ "arm,mali-midgard";
|
|
+ reg = <0xffa30000 0x10000>;
|
|
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "JOB", "MMU", "GPU";
|
|
+ clocks = <&cru ACLK_GPU>;
|
|
+ clock-names = "clk_mali";
|
|
+ operating-points = <
|
|
+ /* KHz uV */
|
|
+ 100000 950000
|
|
+ 200000 950000
|
|
+ 300000 1000000
|
|
+ 400000 1100000
|
|
+ 500000 1200000
|
|
+ 600000 1250000
|
|
+ >;
|
|
+ #cooling-cells = <2>; /* min followed by max */
|
|
+ power-domains = <&power RK3288_PD_GPU>;
|
|
+ status = "disabled";
|
|
+
|
|
+
|
|
+ gpu_power_model: power_model {
|
|
+ compatible = "arm,mali-simple-power-model";
|
|
+ voltage = <950>;
|
|
+ frequency = <500>;
|
|
+ static-power = <300>;
|
|
+ dynamic-power = <396>;
|
|
+ ts = <32000 4700 (-80) 2>;
|
|
+ thermal-zone = "gpu_thermal";
|
|
+ };
|
|
+
|
|
+ };
|
|
+
|
|
reserved-memory {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
@@ -236,6 +360,8 @@
|
|
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
|
fifo-depth = <0x100>;
|
|
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
reg = <0xff0c0000 0x4000>;
|
|
resets = <&cru SRST_MMC0>;
|
|
reset-names = "reset";
|
|
@@ -250,6 +376,8 @@
|
|
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
|
fifo-depth = <0x100>;
|
|
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
reg = <0xff0d0000 0x4000>;
|
|
resets = <&cru SRST_SDIO0>;
|
|
reset-names = "reset";
|
|
@@ -264,6 +392,8 @@
|
|
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
|
fifo-depth = <0x100>;
|
|
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
reg = <0xff0e0000 0x4000>;
|
|
resets = <&cru SRST_SDIO1>;
|
|
reset-names = "reset";
|
|
@@ -278,6 +408,8 @@
|
|
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
|
fifo-depth = <0x100>;
|
|
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
reg = <0xff0f0000 0x4000>;
|
|
resets = <&cru SRST_EMMC>;
|
|
reset-names = "reset";
|
|
@@ -334,9 +466,9 @@
|
|
dma-names = "tx", "rx";
|
|
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
- pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
|
|
+ pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0 &spi2_cs1>;
|
|
reg = <0xff130000 0x1000>;
|
|
- #address-cells = <1>;
|
|
+ #address-cells = <2>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
@@ -527,7 +659,7 @@
|
|
map0 {
|
|
trip = <&gpu_alert0>;
|
|
cooling-device =
|
|
- <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
+ <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
};
|
|
};
|
|
@@ -914,7 +1046,7 @@
|
|
status = "disabled";
|
|
};
|
|
|
|
- spdif: sound@ff88b0000 {
|
|
+ spdif: sound@ff8b0000 {
|
|
compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
|
|
reg = <0xff8b0000 0x10000>;
|
|
#sound-dai-cells = <0>;
|
|
@@ -958,9 +1090,24 @@
|
|
status = "okay";
|
|
};
|
|
|
|
+ rga: rga@ff920000 {
|
|
+ compatible = "rockchip,rk3288-rga";
|
|
+ reg = <0xff920000 0x180>;
|
|
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "rga";
|
|
+ clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
|
|
+ clock-names = "aclk", "hclk", "sclk";
|
|
+ power-domains = <&power RK3288_PD_VIO>;
|
|
+ resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
|
|
+
|
|
+ reset-names = "core", "axi", "ahb";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+
|
|
vopb: vop@ff930000 {
|
|
compatible = "rockchip,rk3288-vop";
|
|
- reg = <0xff930000 0x19c>;
|
|
+ reg = <0xff930000 0x19c>, <0xff931000 0x1000>;
|
|
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
|
|
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
|
|
@@ -1003,7 +1150,7 @@
|
|
|
|
vopl: vop@ff940000 {
|
|
compatible = "rockchip,rk3288-vop";
|
|
- reg = <0xff940000 0x19c>;
|
|
+ reg = <0xff940000 0x19c>, <0xff941000 0x1000>;
|
|
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
|
|
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
|
|
@@ -1078,6 +1225,7 @@
|
|
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
|
|
clock-names = "dp", "pclk";
|
|
+ power-domains = <&power RK3288_PD_VIO>;
|
|
phys = <&edp_phy>;
|
|
phy-names = "dp";
|
|
resets = <&cru SRST_EDP>;
|
|
@@ -1131,48 +1279,6 @@
|
|
};
|
|
};
|
|
|
|
- gpu: mali@ffa30000 {
|
|
- compatible = "rockchip,rk3288-mali", "arm,mali-t760", "arm,mali-midgard";
|
|
- reg = <0xffa30000 0x10000>;
|
|
- interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
|
- interrupt-names = "job", "mmu", "gpu";
|
|
- clocks = <&cru ACLK_GPU>;
|
|
- operating-points-v2 = <&gpu_opp_table>;
|
|
- power-domains = <&power RK3288_PD_GPU>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- gpu_opp_table: gpu-opp-table {
|
|
- compatible = "operating-points-v2";
|
|
-
|
|
- opp@100000000 {
|
|
- opp-hz = /bits/ 64 <100000000>;
|
|
- opp-microvolt = <950000>;
|
|
- };
|
|
- opp@200000000 {
|
|
- opp-hz = /bits/ 64 <200000000>;
|
|
- opp-microvolt = <950000>;
|
|
- };
|
|
- opp@300000000 {
|
|
- opp-hz = /bits/ 64 <300000000>;
|
|
- opp-microvolt = <1000000>;
|
|
- };
|
|
- opp@400000000 {
|
|
- opp-hz = /bits/ 64 <400000000>;
|
|
- opp-microvolt = <1100000>;
|
|
- };
|
|
- opp@500000000 {
|
|
- opp-hz = /bits/ 64 <500000000>;
|
|
- opp-microvolt = <1200000>;
|
|
- };
|
|
- opp@600000000 {
|
|
- opp-hz = /bits/ 64 <600000000>;
|
|
- opp-microvolt = <1250000>;
|
|
- };
|
|
- };
|
|
-
|
|
qos_gpu_r: qos@ffaa0000 {
|
|
compatible = "syscon";
|
|
reg = <0xffaa0000 0x20>;
|