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https://github.com/Fishwaldo/build.git
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a57ce78b37
* Bump to 4.18, removing the obvious, fixing build problems, put some on waiting. * Pin 4.18 to DEV, rollback 4.14 to NEXT, adjust configs, remove one deprecated patch from NEXT and add board-h3-address-some-stability-issues.patch * Adjust few boards in development to new reality, removing it from NEXT for now * Adjust few board configs * Board config adjustement * Adjust few boards configs * Port NeoCore2 and Neo21.1 to 4.14.y * Adjust board config * Adjust board config
64 lines
2.1 KiB
Diff
64 lines
2.1 KiB
Diff
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
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index ee9c12cf3f08..d0e30192f0cf 100644
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--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
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+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
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@@ -64,17 +64,18 @@ static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
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BIT(28), /* lock */
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CLK_SET_RATE_UNGATE);
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-static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0",
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- "osc24M", 0x010,
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- 8, 7, /* N */
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- 0, 4, /* M */
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- BIT(24), /* frac enable */
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- BIT(25), /* frac select */
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- 270000000, /* frac rate 0 */
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- 297000000, /* frac rate 1 */
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- BIT(31), /* gate */
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- BIT(28), /* lock */
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- CLK_SET_RATE_UNGATE);
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+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video0_clk, "pll-video0",
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+ "osc24M", 0x010,
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+ 192000000, /* Minimum rate */
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+ 8, 7, /* N */
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+ 0, 4, /* M */
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+ BIT(24), /* frac enable */
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+ BIT(25), /* frac select */
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+ 270000000, /* frac rate 0 */
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+ 297000000, /* frac rate 1 */
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+ BIT(31), /* gate */
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+ BIT(28), /* lock */
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+ CLK_SET_RATE_UNGATE);
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static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
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"osc24M", 0x018,
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@@ -125,17 +126,18 @@ static struct ccu_nk pll_periph1_clk = {
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},
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};
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-static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1",
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- "osc24M", 0x030,
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- 8, 7, /* N */
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- 0, 4, /* M */
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- BIT(24), /* frac enable */
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- BIT(25), /* frac select */
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- 270000000, /* frac rate 0 */
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- 297000000, /* frac rate 1 */
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- BIT(31), /* gate */
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- BIT(28), /* lock */
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- CLK_SET_RATE_UNGATE);
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+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video1_clk, "pll-video1",
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+ "osc24M", 0x030,
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+ 192000000, /* Minimum rate */
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+ 8, 7, /* N */
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+ 0, 4, /* M */
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+ BIT(24), /* frac enable */
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+ BIT(25), /* frac select */
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+ 270000000, /* frac rate 0 */
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+ 297000000, /* frac rate 1 */
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+ BIT(31), /* gate */
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+ BIT(28), /* lock */
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+ CLK_SET_RATE_UNGATE);
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static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
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"osc24M", 0x038,
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