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a57ce78b37
* Bump to 4.18, removing the obvious, fixing build problems, put some on waiting. * Pin 4.18 to DEV, rollback 4.14 to NEXT, adjust configs, remove one deprecated patch from NEXT and add board-h3-address-some-stability-issues.patch * Adjust few boards in development to new reality, removing it from NEXT for now * Adjust few board configs * Board config adjustement * Adjust few boards configs * Port NeoCore2 and Neo21.1 to 4.14.y * Adjust board config * Adjust board config
45 lines
1.4 KiB
Diff
45 lines
1.4 KiB
Diff
From cb4faa1940f5a33c2406c03476cf37ccc32f1997 Mon Sep 17 00:00:00 2001
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From: Ondrej Jirman <megous@megous.com>
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Date: Sun, 26 Feb 2017 16:09:28 +0100
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Subject: [PATCH 41/87] ARM: sunxi: h3/h5: Add r_i2c I2C controller
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Allwinner H3/H5 SoCs have an I2C controller at PL GPIO bank.
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Add support for it in the device tree.
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Signed-off-by: Ondrej Jirman <megous@megous.com>
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[Icenowy: Change to use r_ccu and change pinmux node name]
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Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
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Reviewed-by: Chen-Yu Tsai <wens@csie.org>
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---
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arch/arm/boot/dts/sunxi-h3-h5.dtsi | 14 ++++++++++++++
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1 file changed, 14 insertions(+)
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diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
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index 3a5f2aad7449..19fb71d29159 100644
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--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
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+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
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@@ -624,6 +624,20 @@
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status = "disabled";
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};
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+ r_i2c: i2c@01f02400 {
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+ compatible = "allwinner,sun6i-a31-i2c";
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+ reg = <0x01f02400 0x400>;
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+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&r_i2c_pins>;
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+ clocks = <&r_ccu CLK_APB0_I2C>;
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+ clock-frequency = <100000>;
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+ resets = <&r_ccu RST_APB0_I2C>;
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+ status = "disabled";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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r_pio: pinctrl@01f02c00 {
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compatible = "allwinner,sun8i-h3-r-pinctrl";
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reg = <0x01f02c00 0x400>;
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--
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2.13.5
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