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e71d1560f0
* helios4: next branch use u-boot 2018
use new u-boot based on upstream 2018
Signed-off-by: Aditya Prayoga <aditya@kobol.io>
* helios4: Tweak fancontrol configuration
Adjusted MINSTART and MINSTOP to suit both old and new fan.
Adjusted TEMP threshold so fan would stop or run in minimal speed when
the system idle.
Fixed wrong MINPWM value.
URL:https://wiki.kobol.io/pwm/#configuration-file
Signed-off-by: Aditya Prayoga <aditya@kobol.io>
* kernel: mvebu-next: use upstream helios4 dts
Helios4 device tree has been merged on upstream since 4.19.
Rework the patch to produce same device tree.
URL:https://patchwork.kernel.org/patch/10449393/
Signed-off-by: Aditya Prayoga <aditya@kobol.io>
* Helios4: Use boot-mvebu-next bootscript
Use boot-mvebu-next.cmd that make use of upstream's Generic Distro
Configuration.
Since loadaddr and fdt_addr varibales are no longer required, remove the
patch.
Signed-off-by: Aditya Prayoga <aditya@kobol.io>
* Helios4: mvebu-next: Add workaround for SPI and SATA concurrent access issue
Concurrent access on SPI NOR and SATA drives can lead to unstable SATA.
Therefore as workaround, disable SATA controller when SPI flash access
is needed and make it as user configurable item in armbianEnv.txt
This workaround might applies to Clearfog too.
Refer to
Commit 59af84c07c ("Helios4: Add SPI bootloader install feature
(#1126)")
Signed-off-by: Aditya Prayoga <aditya@kobol.io>
* Bootscripts: Fixed boot-mvebu-next.cmd
The environment setting (armbianEnv.txt) is loaded to RAM located on
${load_addr} but the env import use wrong address (${pxefile_addr_r}).
bootargs still expect ${boot_interface} which carried over from boot-
marvell.cmd. Upstream's distro configuration use ${devtype} instead.
Signed-off-by: Aditya Prayoga <aditya@kobol.io>
210 lines
6.2 KiB
Diff
210 lines
6.2 KiB
Diff
From 187573405d9fd1d070f035806769cfee52224ac9 Mon Sep 17 00:00:00 2001
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Message-Id: <187573405d9fd1d070f035806769cfee52224ac9.1540752056.git.aditya@kobol.io>
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In-Reply-To: <3eb15c0c6a0f26e418074cf3be9490a36f9161fd.1540752056.git.aditya@kobol.io>
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References: <3eb15c0c6a0f26e418074cf3be9490a36f9161fd.1540752056.git.aditya@kobol.io>
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From: Jon Nettleton <jon@solid-run.com>
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Date: Thu, 24 Aug 2017 22:28:06 +0200
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Subject: [PATCH 03/11] mvebu: rtc: Add DM driver for mvebu rtc
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This is heavily based on the linux kernel driver. Please note the
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long timeout I have added. I have found that adding this additional
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time fixes a lot of the other timing problems that were worked around
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with various delays and repeated commands.
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Signed-off-by: Jon Nettleton <jon@solid-run.com>
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---
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drivers/rtc/Kconfig | 7 +++
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drivers/rtc/Makefile | 1 +
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drivers/rtc/mvebu_rtc.c | 151 ++++++++++++++++++++++++++++++++++++++++++++++++
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3 files changed, 159 insertions(+)
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diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
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index bcc01b1..59b3d2c 100644
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--- a/drivers/rtc/Kconfig
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+++ b/drivers/rtc/Kconfig
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@@ -31,6 +31,13 @@ config TPL_DM_RTC
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drivers to perform the actual functions. See rtc.h for a
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description of the API.
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+config RTC_MVEBU
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+ bool "Armada 38x Marvell SoC RTC"
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+ depends on DM_RTC
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+ help
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+ If you say yes here you will get support for the in-chip RTC
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+ that can be found in the Armada 38x Marvell's SoC device
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+
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config RTC_PCF2127
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bool "Enable PCF2127 driver"
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depends on DM_RTC
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diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
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index 1724602..0e23190 100644
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--- a/drivers/rtc/Makefile
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+++ b/drivers/rtc/Makefile
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@@ -38,6 +38,7 @@ obj-$(CONFIG_RTC_MCP79411) += ds1307.o
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obj-$(CONFIG_MCFRTC) += mcfrtc.o
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obj-$(CONFIG_RTC_MK48T59) += mk48t59.o
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obj-$(CONFIG_RTC_MV) += mvrtc.o
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+obj-$(CONFIG_RTC_MVEBU) += mvebu_rtc.o
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obj-$(CONFIG_RTC_MX27) += mx27rtc.o
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obj-$(CONFIG_RTC_MXS) += mxsrtc.o
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obj-$(CONFIG_RTC_PCF8563) += pcf8563.o
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diff --git a/drivers/rtc/mvebu_rtc.c b/drivers/rtc/mvebu_rtc.c
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new file mode 100644
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index 0000000..b04d8e6
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--- /dev/null
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+++ b/drivers/rtc/mvebu_rtc.c
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@@ -0,0 +1,151 @@
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+/*
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+ * (C) Copyright 2015 Solid Run Ltd.
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+ * Author: Jon Nettleton <jon@solid-run.com>
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+ *
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+ * Based on Linux Kernel driver rtc-armada38x.c
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+ * Copyright (C) 2015 Marvell
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+ * Gregory Clement <gregory.clement@free-electrons.com>
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+ *
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+ * SPDX-License-Identifier: GPL-2.0+
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+ */
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+
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+#include <common.h>
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+#include <asm/io.h>
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+#include <dm.h>
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+#include <rtc.h>
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+
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+DECLARE_GLOBAL_DATA_PTR;
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+
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+#define RTC_NOMINAL_TIMING 0x2000
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+
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+#define RTC_STATUS 0x0
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+#define RTC_STATUS_ALARM1 BIT(0)
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+#define RTC_STATUS_ALARM2 BIT(1)
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+#define RTC_TIME 0xC
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+#define RTC_ALARM1 0x10
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+#define RTC_CLOCK_CORR 0x18
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+#define RTC_TEST_CONF 0x1C
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+
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+/* armada38x SoC registers */
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+#define RTC_38X_BRIDGE_TIMING_CTRL_REG_OFFS 0x0
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+#define RTC_38X_WRCLK_PERIOD_OFFS 0
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+#define RTC_38X_WRCLK_PERIOD_MASK (0x3FF << RTC_38X_WRCLK_PERIOD_OFFS)
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+#define RTC_38X_READ_OUTPUT_DELAY_OFFS 26
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+#define RTC_38X_READ_OUTPUT_DELAY_MASK (0x1F << RTC_38X_READ_OUTPUT_DELAY_OFFS)
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+
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+struct mvebu_rtc_platdata {
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+ fdt_addr_t base;
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+ fdt_addr_t soc_base;
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+};
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+
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+/*
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+ * According to the datasheet, the OS should wait 5us after every
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+ * register write to the RTC hard macro so that the required update
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+ * can occur without holding off the system bus
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+ * According to errata FE-3124064, Write to any RTC register
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+ * may fail. As a workaround, before writing to RTC
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+ * register, issue a dummy write of 0x0 twice to RTC Status
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+ * register.
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+ */
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+
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+static void rtc_delayed_write(u32 val, struct mvebu_rtc_platdata *rtc, int offset)
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+{
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+ writel(0, rtc->base + RTC_STATUS);
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+ writel(0, rtc->base + RTC_STATUS);
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+ writel(val, rtc->base + offset);
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+ mdelay(10);
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+}
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+
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+static unsigned long read_rtc_reg(struct mvebu_rtc_platdata *rtc, uint8_t rtc_reg)
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+{
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+ unsigned long value = readl(rtc->base + rtc_reg);
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+
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+ return value;
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+}
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+
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+static void rtc_update_38x_mbus_timing_params(struct mvebu_rtc_platdata *rtc)
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+{
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+ uint32_t reg;
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+
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+ reg = readl(rtc->soc_base + RTC_38X_BRIDGE_TIMING_CTRL_REG_OFFS);
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+ reg &= ~RTC_38X_WRCLK_PERIOD_MASK;
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+ reg |= 0x3FF << RTC_38X_WRCLK_PERIOD_OFFS; /*Maximum value*/
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+ reg &= ~RTC_38X_READ_OUTPUT_DELAY_MASK;
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+ reg |= 0x1F << RTC_38X_READ_OUTPUT_DELAY_OFFS; /*Maximum value*/
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+ writel(reg, rtc->soc_base + RTC_38X_BRIDGE_TIMING_CTRL_REG_OFFS);
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+}
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+
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+static int mvebu_rtc_get(struct udevice *dev, struct rtc_time *tm)
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+{
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+ struct mvebu_rtc_platdata *rtc = dev_get_platdata(dev);
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+
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+ rtc_to_tm(read_rtc_reg(rtc, RTC_TIME), tm);
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+
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+ return 0;
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+}
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+
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+static int mvebu_rtc_set(struct udevice *dev, const struct rtc_time *tm)
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+{
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+ struct mvebu_rtc_platdata *rtc = dev_get_platdata(dev);
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+ unsigned long time;
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+
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+ time = rtc_mktime(tm);
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+ rtc_delayed_write(time, rtc, RTC_TIME);
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+
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+ return 0;
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+}
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+
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+static int mvebu_rtc_reset(struct udevice *dev)
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+{
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+ struct mvebu_rtc_platdata *rtc = dev_get_platdata(dev);
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+
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+ rtc_delayed_write(0, rtc, RTC_TEST_CONF);
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+ rtc_delayed_write(0, rtc, RTC_TIME);
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+ rtc_delayed_write((RTC_STATUS_ALARM1 | RTC_STATUS_ALARM2), rtc, RTC_STATUS);
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+ rtc_delayed_write(RTC_NOMINAL_TIMING, rtc, RTC_CLOCK_CORR);
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+
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+ return 0;
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+}
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+
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+static int mvebu_rtc_read8(struct udevice *dev, unsigned int reg)
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+{
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+ return -ENOSYS;
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+}
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+
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+static int mvebu_rtc_write8(struct udevice *dev, unsigned int reg, int val)
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+{
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+ return -ENOSYS;
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+}
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+
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+static int mvebu_rtc_probe(struct udevice *dev)
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+{
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+ struct mvebu_rtc_platdata *rtc = dev_get_platdata(dev);
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+
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+ rtc->base = devfdt_get_addr(dev);
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+ rtc->soc_base = devfdt_get_addr_name(dev, "rtc-soc");
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+
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+ rtc_update_38x_mbus_timing_params(rtc);
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+
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+ return 0;
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+}
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+
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+static const struct rtc_ops mvebu_rtc_ops = {
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+ .get = mvebu_rtc_get,
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+ .set = mvebu_rtc_set,
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+ .reset = mvebu_rtc_reset,
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+ .read8 = mvebu_rtc_read8,
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+ .write8 = mvebu_rtc_write8,
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+};
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+
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+static const struct udevice_id mvebu_rtc_ids[] = {
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+ { .compatible = "marvell,armada-380-rtc" },
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+ { }
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+};
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+
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+U_BOOT_DRIVER(rtc_mvebu) = {
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+ .name = "rtc-mvebu",
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+ .id = UCLASS_RTC,
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+ .of_match = mvebu_rtc_ids,
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+ .probe = mvebu_rtc_probe,
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+ .ops = &mvebu_rtc_ops,
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+};
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--
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2.7.4
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