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dmfe: enforce consistent timing delay.

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The driver does not always use the same timing for what looks like
the same operations.

- DCR0
  Use the same udelay everywhere for reset. Upper bound is 100 us.
- DCR9
  Use 5us delay for srom clock. 1us delay for phy_write_1bit (writes
  PHY_DATA_[01]) are not changed as they stay withing a 2,5MHz MDIO
  clock range.

Signed-off-by: Francois Romieu <romieu@fr.zoreil.com>
Reviewed-by: Grant Grundler <grundler@parisc-linux.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
françois romieu 2012-04-17 11:11:40 +00:00 • committed by David S. Miller
parent 584c5e2ad3
commit 0c20494050
1 changed files with 5 additions and 1 deletions
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6
drivers/net/ethernet/dec/tulip/dmfe.c
View file

@ -767,7 +767,7 @@ static int dmfe_stop(struct DEVICE *dev)
/* Reset & stop DM910X board */ /* Reset & stop DM910X board */
dw32(DCR0, DM910X_RESET); dw32(DCR0, DM910X_RESET);
udelay(5); udelay(100);
phy_write(ioaddr, db->phy_addr, 0, 0x8000, db->chip_id); phy_write(ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
/* free interrupt */ /* free interrupt */
@ -1601,7 +1601,9 @@ static u16 read_srom_word(void __iomem *ioaddr, int offset)
int i; int i;
dw32(DCR9, CR9_SROM_READ); dw32(DCR9, CR9_SROM_READ);
udelay(5);
dw32(DCR9, CR9_SROM_READ | CR9_SRCS); dw32(DCR9, CR9_SROM_READ | CR9_SRCS);
udelay(5);
/* Send the Read Command 110b */ /* Send the Read Command 110b */
srom_clk_write(ioaddr, SROM_DATA_1); srom_clk_write(ioaddr, SROM_DATA_1);
@ -1615,6 +1617,7 @@ static u16 read_srom_word(void __iomem *ioaddr, int offset)
} }
dw32(DCR9, CR9_SROM_READ | CR9_SRCS); dw32(DCR9, CR9_SROM_READ | CR9_SRCS);
udelay(5);
for (i = 16; i > 0; i--) { for (i = 16; i > 0; i--) {
dw32(DCR9, CR9_SROM_READ | CR9_SRCS | CR9_SRCLK); dw32(DCR9, CR9_SROM_READ | CR9_SRCS | CR9_SRCLK);
@ -1626,6 +1629,7 @@ static u16 read_srom_word(void __iomem *ioaddr, int offset)
} }
dw32(DCR9, CR9_SROM_READ); dw32(DCR9, CR9_SROM_READ);
udelay(5);
return srom_data; return srom_data;
} }