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firmware: xilinx: Use explicit values for all enum values

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Based on discussion at
https://lore.kernel.org/r/20200318125003.GA2727094@kroah.com we got
recommendation to use explicit values for all enum values.
The patch is following this recommendation.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/daeb67ded45d8a8f6a96717d1fb9c84439dd2ae8.1612361627.git.michal.simek@xilinx.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Michal Simek 2021-02-03 15:13:50 +01:00 • committed by Greg Kroah-Hartman
parent 5b06931d7f
commit 1077d4367a
1 changed files with 169 additions and 169 deletions
Download patch file Download diff file Expand all files Collapse all files

338
include/linux/firmware/xlnx-zynqmp.h
View file

@ -64,25 +64,25 @@ enum pm_api_id {
PM_GET_API_VERSION = 1,
PM_SYSTEM_SHUTDOWN = 12,
PM_REQUEST_NODE = 13,
PM_RELEASE_NODE,
PM_SET_REQUIREMENT,
PM_RELEASE_NODE = 14,
PM_SET_REQUIREMENT = 15,
PM_RESET_ASSERT = 17,
PM_RESET_GET_STATUS,
PM_RESET_GET_STATUS = 18,
PM_PM_INIT_FINALIZE = 21,
PM_FPGA_LOAD,
PM_FPGA_GET_STATUS,
PM_FPGA_LOAD = 22,
PM_FPGA_GET_STATUS = 23,
PM_GET_CHIPID = 24,
PM_IOCTL = 34,
PM_QUERY_DATA,
PM_CLOCK_ENABLE,
PM_CLOCK_DISABLE,
PM_CLOCK_GETSTATE,
PM_CLOCK_SETDIVIDER,
PM_CLOCK_GETDIVIDER,
PM_CLOCK_SETRATE,
PM_CLOCK_GETRATE,
PM_CLOCK_SETPARENT,
PM_CLOCK_GETPARENT,
PM_QUERY_DATA = 35,
PM_CLOCK_ENABLE = 36,
PM_CLOCK_DISABLE = 37,
PM_CLOCK_GETSTATE = 38,
PM_CLOCK_SETDIVIDER = 39,
PM_CLOCK_GETDIVIDER = 40,
PM_CLOCK_SETRATE = 41,
PM_CLOCK_GETRATE = 42,
PM_CLOCK_SETPARENT = 43,
PM_CLOCK_GETPARENT = 44,
PM_SECURE_AES = 47,
PM_FEATURE_CHECK = 63,
};
@ -92,21 +92,21 @@ enum pm_ret_status {
XST_PM_SUCCESS = 0,
XST_PM_NO_FEATURE = 19,
XST_PM_INTERNAL = 2000,
XST_PM_CONFLICT,
XST_PM_NO_ACCESS,
XST_PM_INVALID_NODE,
XST_PM_DOUBLE_REQ,
XST_PM_ABORT_SUSPEND,
XST_PM_CONFLICT = 2001,
XST_PM_NO_ACCESS = 2002,
XST_PM_INVALID_NODE = 2003,
XST_PM_DOUBLE_REQ = 2004,
XST_PM_ABORT_SUSPEND = 2005,
XST_PM_MULT_USER = 2008,
};
enum pm_ioctl_id {
IOCTL_SD_DLL_RESET = 6,
IOCTL_SET_SD_TAPDELAY,
IOCTL_SET_PLL_FRAC_MODE,
IOCTL_GET_PLL_FRAC_MODE,
IOCTL_SET_PLL_FRAC_DATA,
IOCTL_GET_PLL_FRAC_DATA,
IOCTL_SET_SD_TAPDELAY = 7,
IOCTL_SET_PLL_FRAC_MODE = 8,
IOCTL_GET_PLL_FRAC_MODE = 9,
IOCTL_SET_PLL_FRAC_DATA = 10,
IOCTL_GET_PLL_FRAC_DATA = 11,
IOCTL_WRITE_GGS = 12,
IOCTL_READ_GGS = 13,
IOCTL_WRITE_PGGS = 14,
@ -116,185 +116,185 @@ enum pm_ioctl_id {
};
enum pm_query_id {
PM_QID_INVALID,
PM_QID_CLOCK_GET_NAME,
PM_QID_CLOCK_GET_TOPOLOGY,
PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS,
PM_QID_CLOCK_GET_PARENTS,
PM_QID_CLOCK_GET_ATTRIBUTES,
PM_QID_INVALID = 0,
PM_QID_CLOCK_GET_NAME = 1,
PM_QID_CLOCK_GET_TOPOLOGY = 2,
PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS = 3,
PM_QID_CLOCK_GET_PARENTS = 4,
PM_QID_CLOCK_GET_ATTRIBUTES = 5,
PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
PM_QID_CLOCK_GET_MAX_DIVISOR,
PM_QID_CLOCK_GET_MAX_DIVISOR = 13,
};
enum zynqmp_pm_reset_action {
PM_RESET_ACTION_RELEASE,
PM_RESET_ACTION_ASSERT,
PM_RESET_ACTION_PULSE,
PM_RESET_ACTION_RELEASE = 0,
PM_RESET_ACTION_ASSERT = 1,
PM_RESET_ACTION_PULSE = 2,
};
enum zynqmp_pm_reset {
ZYNQMP_PM_RESET_START = 1000,
ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START,
ZYNQMP_PM_RESET_PCIE_BRIDGE,
ZYNQMP_PM_RESET_PCIE_CTRL,
ZYNQMP_PM_RESET_DP,
ZYNQMP_PM_RESET_SWDT_CRF,
ZYNQMP_PM_RESET_AFI_FM5,
ZYNQMP_PM_RESET_AFI_FM4,
ZYNQMP_PM_RESET_AFI_FM3,
ZYNQMP_PM_RESET_AFI_FM2,
ZYNQMP_PM_RESET_AFI_FM1,
ZYNQMP_PM_RESET_AFI_FM0,
ZYNQMP_PM_RESET_GDMA,
ZYNQMP_PM_RESET_GPU_PP1,
ZYNQMP_PM_RESET_GPU_PP0,
ZYNQMP_PM_RESET_GPU,
ZYNQMP_PM_RESET_GT,
ZYNQMP_PM_RESET_SATA,
ZYNQMP_PM_RESET_ACPU3_PWRON,
ZYNQMP_PM_RESET_ACPU2_PWRON,
ZYNQMP_PM_RESET_ACPU1_PWRON,
ZYNQMP_PM_RESET_ACPU0_PWRON,
ZYNQMP_PM_RESET_APU_L2,
ZYNQMP_PM_RESET_ACPU3,
ZYNQMP_PM_RESET_ACPU2,
ZYNQMP_PM_RESET_ACPU1,
ZYNQMP_PM_RESET_ACPU0,
ZYNQMP_PM_RESET_DDR,
ZYNQMP_PM_RESET_APM_FPD,
ZYNQMP_PM_RESET_SOFT,
ZYNQMP_PM_RESET_GEM0,
ZYNQMP_PM_RESET_GEM1,
ZYNQMP_PM_RESET_GEM2,
ZYNQMP_PM_RESET_GEM3,
ZYNQMP_PM_RESET_QSPI,
ZYNQMP_PM_RESET_UART0,
ZYNQMP_PM_RESET_UART1,
ZYNQMP_PM_RESET_SPI0,
ZYNQMP_PM_RESET_SPI1,
ZYNQMP_PM_RESET_SDIO0,
ZYNQMP_PM_RESET_SDIO1,
ZYNQMP_PM_RESET_CAN0,
ZYNQMP_PM_RESET_CAN1,
ZYNQMP_PM_RESET_I2C0,
ZYNQMP_PM_RESET_I2C1,
ZYNQMP_PM_RESET_TTC0,
ZYNQMP_PM_RESET_TTC1,
ZYNQMP_PM_RESET_TTC2,
ZYNQMP_PM_RESET_TTC3,
ZYNQMP_PM_RESET_SWDT_CRL,
ZYNQMP_PM_RESET_NAND,
ZYNQMP_PM_RESET_ADMA,
ZYNQMP_PM_RESET_GPIO,
ZYNQMP_PM_RESET_IOU_CC,
ZYNQMP_PM_RESET_TIMESTAMP,
ZYNQMP_PM_RESET_RPU_R50,
ZYNQMP_PM_RESET_RPU_R51,
ZYNQMP_PM_RESET_RPU_AMBA,
ZYNQMP_PM_RESET_OCM,
ZYNQMP_PM_RESET_RPU_PGE,
ZYNQMP_PM_RESET_USB0_CORERESET,
ZYNQMP_PM_RESET_USB1_CORERESET,
ZYNQMP_PM_RESET_USB0_HIBERRESET,
ZYNQMP_PM_RESET_USB1_HIBERRESET,
ZYNQMP_PM_RESET_USB0_APB,
ZYNQMP_PM_RESET_USB1_APB,
ZYNQMP_PM_RESET_IPI,
ZYNQMP_PM_RESET_APM_LPD,
ZYNQMP_PM_RESET_RTC,
ZYNQMP_PM_RESET_SYSMON,
ZYNQMP_PM_RESET_AFI_FM6,
ZYNQMP_PM_RESET_LPD_SWDT,
ZYNQMP_PM_RESET_FPD,
ZYNQMP_PM_RESET_RPU_DBG1,
ZYNQMP_PM_RESET_RPU_DBG0,
ZYNQMP_PM_RESET_DBG_LPD,
ZYNQMP_PM_RESET_DBG_FPD,
ZYNQMP_PM_RESET_APLL,
ZYNQMP_PM_RESET_DPLL,
ZYNQMP_PM_RESET_VPLL,
ZYNQMP_PM_RESET_IOPLL,
ZYNQMP_PM_RESET_RPLL,
ZYNQMP_PM_RESET_GPO3_PL_0,
ZYNQMP_PM_RESET_GPO3_PL_1,
ZYNQMP_PM_RESET_GPO3_PL_2,
ZYNQMP_PM_RESET_GPO3_PL_3,
ZYNQMP_PM_RESET_GPO3_PL_4,
ZYNQMP_PM_RESET_GPO3_PL_5,
ZYNQMP_PM_RESET_GPO3_PL_6,
ZYNQMP_PM_RESET_GPO3_PL_7,
ZYNQMP_PM_RESET_GPO3_PL_8,
ZYNQMP_PM_RESET_GPO3_PL_9,
ZYNQMP_PM_RESET_GPO3_PL_10,
ZYNQMP_PM_RESET_GPO3_PL_11,
ZYNQMP_PM_RESET_GPO3_PL_12,
ZYNQMP_PM_RESET_GPO3_PL_13,
ZYNQMP_PM_RESET_GPO3_PL_14,
ZYNQMP_PM_RESET_GPO3_PL_15,
ZYNQMP_PM_RESET_GPO3_PL_16,
ZYNQMP_PM_RESET_GPO3_PL_17,
ZYNQMP_PM_RESET_GPO3_PL_18,
ZYNQMP_PM_RESET_GPO3_PL_19,
ZYNQMP_PM_RESET_GPO3_PL_20,
ZYNQMP_PM_RESET_GPO3_PL_21,
ZYNQMP_PM_RESET_GPO3_PL_22,
ZYNQMP_PM_RESET_GPO3_PL_23,
ZYNQMP_PM_RESET_GPO3_PL_24,
ZYNQMP_PM_RESET_GPO3_PL_25,
ZYNQMP_PM_RESET_GPO3_PL_26,
ZYNQMP_PM_RESET_GPO3_PL_27,
ZYNQMP_PM_RESET_GPO3_PL_28,
ZYNQMP_PM_RESET_GPO3_PL_29,
ZYNQMP_PM_RESET_GPO3_PL_30,
ZYNQMP_PM_RESET_GPO3_PL_31,
ZYNQMP_PM_RESET_RPU_LS,
ZYNQMP_PM_RESET_PS_ONLY,
ZYNQMP_PM_RESET_PL,
ZYNQMP_PM_RESET_PS_PL0,
ZYNQMP_PM_RESET_PS_PL1,
ZYNQMP_PM_RESET_PS_PL2,
ZYNQMP_PM_RESET_PS_PL3,
ZYNQMP_PM_RESET_PCIE_BRIDGE = 1001,
ZYNQMP_PM_RESET_PCIE_CTRL = 1002,
ZYNQMP_PM_RESET_DP = 1003,
ZYNQMP_PM_RESET_SWDT_CRF = 1004,
ZYNQMP_PM_RESET_AFI_FM5 = 1005,
ZYNQMP_PM_RESET_AFI_FM4 = 1006,
ZYNQMP_PM_RESET_AFI_FM3 = 1007,
ZYNQMP_PM_RESET_AFI_FM2 = 1008,
ZYNQMP_PM_RESET_AFI_FM1 = 1009,
ZYNQMP_PM_RESET_AFI_FM0 = 1010,
ZYNQMP_PM_RESET_GDMA = 1011,
ZYNQMP_PM_RESET_GPU_PP1 = 1012,
ZYNQMP_PM_RESET_GPU_PP0 = 1013,
ZYNQMP_PM_RESET_GPU = 1014,
ZYNQMP_PM_RESET_GT = 1015,
ZYNQMP_PM_RESET_SATA = 1016,
ZYNQMP_PM_RESET_ACPU3_PWRON = 1017,
ZYNQMP_PM_RESET_ACPU2_PWRON = 1018,
ZYNQMP_PM_RESET_ACPU1_PWRON = 1019,
ZYNQMP_PM_RESET_ACPU0_PWRON = 1020,
ZYNQMP_PM_RESET_APU_L2 = 1021,
ZYNQMP_PM_RESET_ACPU3 = 1022,
ZYNQMP_PM_RESET_ACPU2 = 1023,
ZYNQMP_PM_RESET_ACPU1 = 1024,
ZYNQMP_PM_RESET_ACPU0 = 1025,
ZYNQMP_PM_RESET_DDR = 1026,
ZYNQMP_PM_RESET_APM_FPD = 1027,
ZYNQMP_PM_RESET_SOFT = 1028,
ZYNQMP_PM_RESET_GEM0 = 1029,
ZYNQMP_PM_RESET_GEM1 = 1030,
ZYNQMP_PM_RESET_GEM2 = 1031,
ZYNQMP_PM_RESET_GEM3 = 1032,
ZYNQMP_PM_RESET_QSPI = 1033,
ZYNQMP_PM_RESET_UART0 = 1034,
ZYNQMP_PM_RESET_UART1 = 1035,
ZYNQMP_PM_RESET_SPI0 = 1036,
ZYNQMP_PM_RESET_SPI1 = 1037,
ZYNQMP_PM_RESET_SDIO0 = 1038,
ZYNQMP_PM_RESET_SDIO1 = 1039,
ZYNQMP_PM_RESET_CAN0 = 1040,
ZYNQMP_PM_RESET_CAN1 = 1041,
ZYNQMP_PM_RESET_I2C0 = 1042,
ZYNQMP_PM_RESET_I2C1 = 1043,
ZYNQMP_PM_RESET_TTC0 = 1044,
ZYNQMP_PM_RESET_TTC1 = 1045,
ZYNQMP_PM_RESET_TTC2 = 1046,
ZYNQMP_PM_RESET_TTC3 = 1047,
ZYNQMP_PM_RESET_SWDT_CRL = 1048,
ZYNQMP_PM_RESET_NAND = 1049,
ZYNQMP_PM_RESET_ADMA = 1050,
ZYNQMP_PM_RESET_GPIO = 1051,
ZYNQMP_PM_RESET_IOU_CC = 1052,
ZYNQMP_PM_RESET_TIMESTAMP = 1053,
ZYNQMP_PM_RESET_RPU_R50 = 1054,
ZYNQMP_PM_RESET_RPU_R51 = 1055,
ZYNQMP_PM_RESET_RPU_AMBA = 1056,
ZYNQMP_PM_RESET_OCM = 1057,
ZYNQMP_PM_RESET_RPU_PGE = 1058,
ZYNQMP_PM_RESET_USB0_CORERESET = 1059,
ZYNQMP_PM_RESET_USB1_CORERESET = 1060,
ZYNQMP_PM_RESET_USB0_HIBERRESET = 1061,
ZYNQMP_PM_RESET_USB1_HIBERRESET = 1062,
ZYNQMP_PM_RESET_USB0_APB = 1063,
ZYNQMP_PM_RESET_USB1_APB = 1064,
ZYNQMP_PM_RESET_IPI = 1065,
ZYNQMP_PM_RESET_APM_LPD = 1066,
ZYNQMP_PM_RESET_RTC = 1067,
ZYNQMP_PM_RESET_SYSMON = 1068,
ZYNQMP_PM_RESET_AFI_FM6 = 1069,
ZYNQMP_PM_RESET_LPD_SWDT = 1070,
ZYNQMP_PM_RESET_FPD = 1071,
ZYNQMP_PM_RESET_RPU_DBG1 = 1072,
ZYNQMP_PM_RESET_RPU_DBG0 = 1073,
ZYNQMP_PM_RESET_DBG_LPD = 1074,
ZYNQMP_PM_RESET_DBG_FPD = 1075,
ZYNQMP_PM_RESET_APLL = 1076,
ZYNQMP_PM_RESET_DPLL = 1077,
ZYNQMP_PM_RESET_VPLL = 1078,
ZYNQMP_PM_RESET_IOPLL = 1079,
ZYNQMP_PM_RESET_RPLL = 1080,
ZYNQMP_PM_RESET_GPO3_PL_0 = 1081,
ZYNQMP_PM_RESET_GPO3_PL_1 = 1082,
ZYNQMP_PM_RESET_GPO3_PL_2 = 1083,
ZYNQMP_PM_RESET_GPO3_PL_3 = 1084,
ZYNQMP_PM_RESET_GPO3_PL_4 = 1085,
ZYNQMP_PM_RESET_GPO3_PL_5 = 1086,
ZYNQMP_PM_RESET_GPO3_PL_6 = 1087,
ZYNQMP_PM_RESET_GPO3_PL_7 = 1088,
ZYNQMP_PM_RESET_GPO3_PL_8 = 1089,
ZYNQMP_PM_RESET_GPO3_PL_9 = 1090,
ZYNQMP_PM_RESET_GPO3_PL_10 = 1091,
ZYNQMP_PM_RESET_GPO3_PL_11 = 1092,
ZYNQMP_PM_RESET_GPO3_PL_12 = 1093,
ZYNQMP_PM_RESET_GPO3_PL_13 = 1094,
ZYNQMP_PM_RESET_GPO3_PL_14 = 1095,
ZYNQMP_PM_RESET_GPO3_PL_15 = 1096,
ZYNQMP_PM_RESET_GPO3_PL_16 = 1097,
ZYNQMP_PM_RESET_GPO3_PL_17 = 1098,
ZYNQMP_PM_RESET_GPO3_PL_18 = 1099,
ZYNQMP_PM_RESET_GPO3_PL_19 = 1100,
ZYNQMP_PM_RESET_GPO3_PL_20 = 1101,
ZYNQMP_PM_RESET_GPO3_PL_21 = 1102,
ZYNQMP_PM_RESET_GPO3_PL_22 = 1103,
ZYNQMP_PM_RESET_GPO3_PL_23 = 1104,
ZYNQMP_PM_RESET_GPO3_PL_24 = 1105,
ZYNQMP_PM_RESET_GPO3_PL_25 = 1106,
ZYNQMP_PM_RESET_GPO3_PL_26 = 1107,
ZYNQMP_PM_RESET_GPO3_PL_27 = 1108,
ZYNQMP_PM_RESET_GPO3_PL_28 = 1109,
ZYNQMP_PM_RESET_GPO3_PL_29 = 1110,
ZYNQMP_PM_RESET_GPO3_PL_30 = 1111,
ZYNQMP_PM_RESET_GPO3_PL_31 = 1112,
ZYNQMP_PM_RESET_RPU_LS = 1113,
ZYNQMP_PM_RESET_PS_ONLY = 1114,
ZYNQMP_PM_RESET_PL = 1115,
ZYNQMP_PM_RESET_PS_PL0 = 1116,
ZYNQMP_PM_RESET_PS_PL1 = 1117,
ZYNQMP_PM_RESET_PS_PL2 = 1118,
ZYNQMP_PM_RESET_PS_PL3 = 1119,
ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3
};
enum zynqmp_pm_suspend_reason {
SUSPEND_POWER_REQUEST = 201,
SUSPEND_ALERT,
SUSPEND_SYSTEM_SHUTDOWN,
SUSPEND_ALERT = 202,
SUSPEND_SYSTEM_SHUTDOWN = 203,
};
enum zynqmp_pm_request_ack {
ZYNQMP_PM_REQUEST_ACK_NO = 1,
ZYNQMP_PM_REQUEST_ACK_BLOCKING,
ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING,
ZYNQMP_PM_REQUEST_ACK_BLOCKING = 2,
ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING = 3,
};
enum pm_node_id {
NODE_SD_0 = 39,
NODE_SD_1,
NODE_SD_1 = 40,
};
enum tap_delay_type {
PM_TAPDELAY_INPUT = 0,
PM_TAPDELAY_OUTPUT,
PM_TAPDELAY_OUTPUT = 1,
};
enum dll_reset_type {
PM_DLL_RESET_ASSERT,
PM_DLL_RESET_RELEASE,
PM_DLL_RESET_PULSE,
PM_DLL_RESET_ASSERT = 0,
PM_DLL_RESET_RELEASE = 1,
PM_DLL_RESET_PULSE = 2,
};
enum zynqmp_pm_shutdown_type {
ZYNQMP_PM_SHUTDOWN_TYPE_SHUTDOWN,
ZYNQMP_PM_SHUTDOWN_TYPE_RESET,
ZYNQMP_PM_SHUTDOWN_TYPE_SETSCOPE_ONLY,
ZYNQMP_PM_SHUTDOWN_TYPE_SHUTDOWN = 0,
ZYNQMP_PM_SHUTDOWN_TYPE_RESET = 1,
ZYNQMP_PM_SHUTDOWN_TYPE_SETSCOPE_ONLY = 2,
};
enum zynqmp_pm_shutdown_subtype {
ZYNQMP_PM_SHUTDOWN_SUBTYPE_SUBSYSTEM,
ZYNQMP_PM_SHUTDOWN_SUBTYPE_PS_ONLY,
ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM,
ZYNQMP_PM_SHUTDOWN_SUBTYPE_SUBSYSTEM = 0,
ZYNQMP_PM_SHUTDOWN_SUBTYPE_PS_ONLY = 1,
ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM = 2,
};
/**