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Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

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Pull MIPS fixes from Ralf Baechle:
 "Resurrect Alchemy platforms by invoking the WAIT instructions with
  interrupts enabled.  This still leaves the race condition between
  testing TIF_NEED_RESCHED and the WAIT instruction for Alchemy
  platforms which need a different fix than other MIPS platforms.  But
  at least it gets MIPS platforms flying again.

  There are also fixes for two build errors (CONFIG_FTRACE=y with
  CONFIG_DYNAMIC_FTRACE=n) and CONFIG_VIRTUALIZATION without CONFIG_KVM"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
  MIPS: ftrace: Add missing CONFIG_DYNAMIC_FTRACE
  MIPS: include: mmu_context.h: Replace VIRTUALIZATION with KVM
  MIPS: Alchemy: fix wait function
This commit is contained in:
Linus Torvalds 2013-06-12 11:48:14 -07:00
commit 1a9c3d68d6
3 changed files with 12 additions and 7 deletions
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2
arch/mips/include/asm/mmu_context.h
View file

@ -117,7 +117,7 @@ get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
if (! ((asid += ASID_INC) & ASID_MASK) ) { if (! ((asid += ASID_INC) & ASID_MASK) ) {
if (cpu_has_vtag_icache) if (cpu_has_vtag_icache)
flush_icache_all(); flush_icache_all();
#ifdef CONFIG_VIRTUALIZATION #ifdef CONFIG_KVM
kvm_local_flush_tlb_all(); /* start new asid cycle */ kvm_local_flush_tlb_all(); /* start new asid cycle */
#else #else
local_flush_tlb_all(); /* start new asid cycle */ local_flush_tlb_all(); /* start new asid cycle */

4
arch/mips/kernel/ftrace.c
View file

@ -25,12 +25,16 @@
#define MCOUNT_OFFSET_INSNS 4 #define MCOUNT_OFFSET_INSNS 4
#endif #endif
#ifdef CONFIG_DYNAMIC_FTRACE
/* Arch override because MIPS doesn't need to run this from stop_machine() */ /* Arch override because MIPS doesn't need to run this from stop_machine() */
void arch_ftrace_update_code(int command) void arch_ftrace_update_code(int command)
{ {
ftrace_modify_all_code(command); ftrace_modify_all_code(command);
} }
#endif
/* /*
* Check if the address is in kernel space * Check if the address is in kernel space
* *

13
arch/mips/kernel/idle.c
View file

@ -93,26 +93,27 @@ static void rm7k_wait_irqoff(void)
} }
/* /*
* The Au1xxx wait is available only if using 32khz counter or * Au1 'wait' is only useful when the 32kHz counter is used as timer,
* external timer source, but specifically not CP0 Counter. * since coreclock (and the cp0 counter) stops upon executing it. Only an
* alchemy/common/time.c may override cpu_wait! * interrupt can wake it, so they must be enabled before entering idle modes.
*/ */
static void au1k_wait(void) static void au1k_wait(void)
{ {
unsigned long c0status = read_c0_status() | 1; /* irqs on */
__asm__( __asm__(
" .set mips3 \n" " .set mips3 \n"
" cache 0x14, 0(%0) \n" " cache 0x14, 0(%0) \n"
" cache 0x14, 32(%0) \n" " cache 0x14, 32(%0) \n"
" sync \n" " sync \n"
" nop \n" " mtc0 %1, $12 \n" /* wr c0status */
" wait \n" " wait \n"
" nop \n" " nop \n"
" nop \n" " nop \n"
" nop \n" " nop \n"
" nop \n" " nop \n"
" .set mips0 \n" " .set mips0 \n"
: : "r" (au1k_wait)); : : "r" (au1k_wait), "r" (c0status));
local_irq_enable();
} }
static int __initdata nowait; static int __initdata nowait;