mirror of
https://github.com/Fishwaldo/linux-bl808.git
synced 2025-06-17 20:25:19 +00:00
- ARM: GICv3 ITS emulation and various fixes. Removal of the old
VGIC implementation. - s390: support for trapping software breakpoints, nested virtualization (vSIE), the STHYI opcode, initial extensions for CPU model support. - MIPS: support for MIPS64 hosts (32-bit guests only) and lots of cleanups, preliminary to this and the upcoming support for hardware virtualization extensions. - x86: support for execute-only mappings in nested EPT; reduced vmexit latency for TSC deadline timer (by about 30%) on Intel hosts; support for more than 255 vCPUs. - PPC: bugfixes. The ugly bit is the conflicts. A couple of them are simple conflicts due to 4.7 fixes, but most of them are with other trees. There was definitely too much reliance on Acked-by here. Some conflicts are for KVM patches where _I_ gave my Acked-by, but the worst are for this pull request's patches that touch files outside arch/*/kvm. KVM submaintainers should probably learn to synchronize better with arch maintainers, with the latter providing topic branches whenever possible instead of Acked-by. This is what we do with arch/x86. And I should learn to refuse pull requests when linux-next sends scary signals, even if that means that submaintainers have to rebase their branches. Anyhow, here's the list: - arch/x86/kvm/vmx.c: handle_pcommit and EXIT_REASON_PCOMMIT was removed by the nvdimm tree. This tree adds handle_preemption_timer and EXIT_REASON_PREEMPTION_TIMER at the same place. In general all mentions of pcommit have to go. There is also a conflict between a stable fix and this patch, where the stable fix removed the vmx_create_pml_buffer function and its call. - virt/kvm/kvm_main.c: kvm_cpu_notifier was removed by the hotplug tree. This tree adds kvm_io_bus_get_dev at the same place. - virt/kvm/arm/vgic.c: a few final bugfixes went into 4.7 before the file was completely removed for 4.8. - include/linux/irqchip/arm-gic-v3.h: this one is entirely our fault; this is a change that should have gone in through the irqchip tree and pulled by kvm-arm. I think I would have rejected this kvm-arm pull request. The KVM version is the right one, except that it lacks GITS_BASER_PAGES_SHIFT. - arch/powerpc: what a mess. For the idle_book3s.S conflict, the KVM tree is the right one; everything else is trivial. In this case I am not quite sure what went wrong. The commit that is causing the mess (fd7bacbca4, "KVM: PPC: Book3S HV: Fix TB corruption in guest exit path on HMI interrupt", 2016-05-15) touches both arch/powerpc/kernel/ and arch/powerpc/kvm/. It's large, but at 396 insertions/5 deletions I guessed that it wasn't really possible to split it and that the 5 deletions wouldn't conflict. That wasn't the case. - arch/s390: also messy. First is hypfs_diag.c where the KVM tree moved some code and the s390 tree patched it. You have to reapply the relevant part of commits6c22c98637, plus all ofe030c1125e, to arch/s390/kernel/diag.c. Or pick the linux-next conflict resolution from http://marc.info/?l=kvm&m=146717549531603&w=2. Second, there is a conflict in gmap.c between a stable fix and 4.8. The KVM version here is the correct one. I have pushed my resolution at refs/heads/merge-20160802 (commit 3d1f53419842) at git://git.kernel.org/pub/scm/virt/kvm/kvm.git. -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.22 (GNU/Linux) iQEcBAABAgAGBQJXoGm7AAoJEL/70l94x66DugQIAIj703ePAFepB/fCrKHkZZia SGrsBdvAtNsOhr7FQ5qvvjLxiv/cv7CymeuJivX8H+4kuUHUllDzey+RPHYHD9X7 U6n1PdCH9F15a3IXc8tDjlDdOMNIKJixYuq1UyNZMU6NFwl00+TZf9JF8A2US65b x/41W98ilL6nNBAsoDVmCLtPNWAqQ3lajaZELGfcqRQ9ZGKcAYOaLFXHv2YHf2XC qIDMf+slBGSQ66UoATnYV2gAopNlWbZ7n0vO6tE2KyvhHZ1m399aBX1+k8la/0JI 69r+Tz7ZHUSFtmlmyByi5IAB87myy2WQHyAPwj+4vwJkDGPcl0TrupzbG7+T05Y= =42ti -----END PGP SIGNATURE----- Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm Pull KVM updates from Paolo Bonzini: - ARM: GICv3 ITS emulation and various fixes. Removal of the old VGIC implementation. - s390: support for trapping software breakpoints, nested virtualization (vSIE), the STHYI opcode, initial extensions for CPU model support. - MIPS: support for MIPS64 hosts (32-bit guests only) and lots of cleanups, preliminary to this and the upcoming support for hardware virtualization extensions. - x86: support for execute-only mappings in nested EPT; reduced vmexit latency for TSC deadline timer (by about 30%) on Intel hosts; support for more than 255 vCPUs. - PPC: bugfixes. * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (302 commits) KVM: PPC: Introduce KVM_CAP_PPC_HTM MIPS: Select HAVE_KVM for MIPS64_R{2,6} MIPS: KVM: Reset CP0_PageMask during host TLB flush MIPS: KVM: Fix ptr->int cast via KVM_GUEST_KSEGX() MIPS: KVM: Sign extend MFC0/RDHWR results MIPS: KVM: Fix 64-bit big endian dynamic translation MIPS: KVM: Fail if ebase doesn't fit in CP0_EBase MIPS: KVM: Use 64-bit CP0_EBase when appropriate MIPS: KVM: Set CP0_Status.KX on MIPS64 MIPS: KVM: Make entry code MIPS64 friendly MIPS: KVM: Use kmap instead of CKSEG0ADDR() MIPS: KVM: Use virt_to_phys() to get commpage PFN MIPS: Fix definition of KSEGX() for 64-bit KVM: VMX: Add VMCS to CPU's loaded VMCSs before VMPTRLD kvm: x86: nVMX: maintain internal copy of current VMCS KVM: PPC: Book3S HV: Save/restore TM state in H_CEDE KVM: PPC: Book3S HV: Pull out TM state save/restore into separate procedures KVM: arm64: vgic-its: Simplify MAPI error handling KVM: arm64: vgic-its: Make vgic_its_cmd_handle_mapi similar to other handlers KVM: arm64: vgic-its: Turn device_id validation into generic ID validation ...
This commit is contained in:
Linus Torvalds
commit
221bb8a46e
167 changed files with 11790 additions and 9297 deletions
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@ -112,34 +112,76 @@
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#define GICR_WAKER_ProcessorSleep (1U << 1)
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#define GICR_WAKER_ChildrenAsleep (1U << 2)
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#define GICR_PROPBASER_NonShareable (0U << 10)
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#define GICR_PROPBASER_InnerShareable (1U << 10)
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#define GICR_PROPBASER_OuterShareable (2U << 10)
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#define GICR_PROPBASER_SHAREABILITY_MASK (3UL << 10)
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#define GICR_PROPBASER_nCnB (0U << 7)
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#define GICR_PROPBASER_nC (1U << 7)
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#define GICR_PROPBASER_RaWt (2U << 7)
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#define GICR_PROPBASER_RaWb (3U << 7)
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#define GICR_PROPBASER_WaWt (4U << 7)
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#define GICR_PROPBASER_WaWb (5U << 7)
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#define GICR_PROPBASER_RaWaWt (6U << 7)
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#define GICR_PROPBASER_RaWaWb (7U << 7)
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#define GICR_PROPBASER_CACHEABILITY_MASK (7U << 7)
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#define GICR_PROPBASER_IDBITS_MASK (0x1f)
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#define GIC_BASER_CACHE_nCnB 0ULL
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#define GIC_BASER_CACHE_SameAsInner 0ULL
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#define GIC_BASER_CACHE_nC 1ULL
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#define GIC_BASER_CACHE_RaWt 2ULL
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#define GIC_BASER_CACHE_RaWb 3ULL
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#define GIC_BASER_CACHE_WaWt 4ULL
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#define GIC_BASER_CACHE_WaWb 5ULL
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#define GIC_BASER_CACHE_RaWaWt 6ULL
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#define GIC_BASER_CACHE_RaWaWb 7ULL
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#define GIC_BASER_CACHE_MASK 7ULL
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#define GIC_BASER_NonShareable 0ULL
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#define GIC_BASER_InnerShareable 1ULL
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#define GIC_BASER_OuterShareable 2ULL
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#define GIC_BASER_SHAREABILITY_MASK 3ULL
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#define GICR_PENDBASER_NonShareable (0U << 10)
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#define GICR_PENDBASER_InnerShareable (1U << 10)
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#define GICR_PENDBASER_OuterShareable (2U << 10)
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#define GICR_PENDBASER_SHAREABILITY_MASK (3UL << 10)
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#define GICR_PENDBASER_nCnB (0U << 7)
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#define GICR_PENDBASER_nC (1U << 7)
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#define GICR_PENDBASER_RaWt (2U << 7)
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#define GICR_PENDBASER_RaWb (3U << 7)
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#define GICR_PENDBASER_WaWt (4U << 7)
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#define GICR_PENDBASER_WaWb (5U << 7)
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#define GICR_PENDBASER_RaWaWt (6U << 7)
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#define GICR_PENDBASER_RaWaWb (7U << 7)
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#define GICR_PENDBASER_CACHEABILITY_MASK (7U << 7)
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#define GIC_BASER_CACHEABILITY(reg, inner_outer, type) \
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(GIC_BASER_CACHE_##type << reg##_##inner_outer##_CACHEABILITY_SHIFT)
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#define GIC_BASER_SHAREABILITY(reg, type) \
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(GIC_BASER_##type << reg##_SHAREABILITY_SHIFT)
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#define GICR_PROPBASER_SHAREABILITY_SHIFT (10)
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#define GICR_PROPBASER_INNER_CACHEABILITY_SHIFT (7)
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#define GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT (56)
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#define GICR_PROPBASER_SHAREABILITY_MASK \
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GIC_BASER_SHAREABILITY(GICR_PROPBASER, SHAREABILITY_MASK)
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#define GICR_PROPBASER_INNER_CACHEABILITY_MASK \
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GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, MASK)
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#define GICR_PROPBASER_OUTER_CACHEABILITY_MASK \
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GIC_BASER_CACHEABILITY(GICR_PROPBASER, OUTER, MASK)
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#define GICR_PROPBASER_CACHEABILITY_MASK GICR_PROPBASER_INNER_CACHEABILITY_MASK
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#define GICR_PROPBASER_InnerShareable \
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GIC_BASER_SHAREABILITY(GICR_PROPBASER, InnerShareable)
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#define GICR_PROPBASER_nCnB GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, nCnB)
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#define GICR_PROPBASER_nC GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, nC)
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#define GICR_PROPBASER_RaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWt)
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#define GICR_PROPBASER_RaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWt)
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#define GICR_PROPBASER_WaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WaWt)
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#define GICR_PROPBASER_WaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WaWb)
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#define GICR_PROPBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWaWt)
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#define GICR_PROPBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWaWb)
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#define GICR_PROPBASER_IDBITS_MASK (0x1f)
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#define GICR_PENDBASER_SHAREABILITY_SHIFT (10)
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#define GICR_PENDBASER_INNER_CACHEABILITY_SHIFT (7)
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#define GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT (56)
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#define GICR_PENDBASER_SHAREABILITY_MASK \
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GIC_BASER_SHAREABILITY(GICR_PENDBASER, SHAREABILITY_MASK)
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#define GICR_PENDBASER_INNER_CACHEABILITY_MASK \
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GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, MASK)
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#define GICR_PENDBASER_OUTER_CACHEABILITY_MASK \
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GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, MASK)
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#define GICR_PENDBASER_CACHEABILITY_MASK GICR_PENDBASER_INNER_CACHEABILITY_MASK
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#define GICR_PENDBASER_InnerShareable \
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GIC_BASER_SHAREABILITY(GICR_PENDBASER, InnerShareable)
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#define GICR_PENDBASER_nCnB GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, nCnB)
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#define GICR_PENDBASER_nC GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, nC)
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#define GICR_PENDBASER_RaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWt)
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#define GICR_PENDBASER_RaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWt)
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#define GICR_PENDBASER_WaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, WaWt)
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#define GICR_PENDBASER_WaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, WaWb)
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#define GICR_PENDBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWaWt)
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#define GICR_PENDBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWaWb)
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#define GICR_PENDBASER_PTZ BIT_ULL(62)
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/*
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* Re-Distributor registers, offsets from SGI_base
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@ -175,54 +217,83 @@
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#define GITS_CWRITER 0x0088
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#define GITS_CREADR 0x0090
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#define GITS_BASER 0x0100
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#define GITS_IDREGS_BASE 0xffd0
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#define GITS_PIDR0 0xffe0
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#define GITS_PIDR1 0xffe4
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#define GITS_PIDR2 GICR_PIDR2
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#define GITS_PIDR4 0xffd0
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#define GITS_CIDR0 0xfff0
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#define GITS_CIDR1 0xfff4
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#define GITS_CIDR2 0xfff8
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#define GITS_CIDR3 0xfffc
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#define GITS_TRANSLATER 0x10040
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#define GITS_CTLR_ENABLE (1U << 0)
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#define GITS_CTLR_QUIESCENT (1U << 31)
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#define GITS_TYPER_PLPIS (1UL << 0)
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#define GITS_TYPER_IDBITS_SHIFT 8
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#define GITS_TYPER_DEVBITS_SHIFT 13
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#define GITS_TYPER_DEVBITS(r) ((((r) >> GITS_TYPER_DEVBITS_SHIFT) & 0x1f) + 1)
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#define GITS_TYPER_PTA (1UL << 19)
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#define GITS_TYPER_HWCOLLCNT_SHIFT 24
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#define GITS_CBASER_VALID (1UL << 63)
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#define GITS_CBASER_nCnB (0UL << 59)
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#define GITS_CBASER_nC (1UL << 59)
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#define GITS_CBASER_RaWt (2UL << 59)
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#define GITS_CBASER_RaWb (3UL << 59)
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#define GITS_CBASER_WaWt (4UL << 59)
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#define GITS_CBASER_WaWb (5UL << 59)
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#define GITS_CBASER_RaWaWt (6UL << 59)
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#define GITS_CBASER_RaWaWb (7UL << 59)
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#define GITS_CBASER_CACHEABILITY_MASK (7UL << 59)
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#define GITS_CBASER_NonShareable (0UL << 10)
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#define GITS_CBASER_InnerShareable (1UL << 10)
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#define GITS_CBASER_OuterShareable (2UL << 10)
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#define GITS_CBASER_SHAREABILITY_MASK (3UL << 10)
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#define GITS_CBASER_VALID (1UL << 63)
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#define GITS_CBASER_SHAREABILITY_SHIFT (10)
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#define GITS_CBASER_INNER_CACHEABILITY_SHIFT (59)
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#define GITS_CBASER_OUTER_CACHEABILITY_SHIFT (53)
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#define GITS_CBASER_SHAREABILITY_MASK \
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GIC_BASER_SHAREABILITY(GITS_CBASER, SHAREABILITY_MASK)
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#define GITS_CBASER_INNER_CACHEABILITY_MASK \
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GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, MASK)
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#define GITS_CBASER_OUTER_CACHEABILITY_MASK \
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GIC_BASER_CACHEABILITY(GITS_CBASER, OUTER, MASK)
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#define GITS_CBASER_CACHEABILITY_MASK GITS_CBASER_INNER_CACHEABILITY_MASK
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#define GITS_CBASER_InnerShareable \
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GIC_BASER_SHAREABILITY(GITS_CBASER, InnerShareable)
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#define GITS_CBASER_nCnB GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, nCnB)
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#define GITS_CBASER_nC GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, nC)
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#define GITS_CBASER_RaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWt)
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#define GITS_CBASER_RaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWt)
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#define GITS_CBASER_WaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, WaWt)
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#define GITS_CBASER_WaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, WaWb)
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#define GITS_CBASER_RaWaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWaWt)
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#define GITS_CBASER_RaWaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWaWb)
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#define GITS_BASER_NR_REGS 8
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#define GITS_BASER_VALID (1UL << 63)
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#define GITS_BASER_INDIRECT (1UL << 62)
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#define GITS_BASER_nCnB (0UL << 59)
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#define GITS_BASER_nC (1UL << 59)
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#define GITS_BASER_RaWt (2UL << 59)
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#define GITS_BASER_RaWb (3UL << 59)
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#define GITS_BASER_WaWt (4UL << 59)
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#define GITS_BASER_WaWb (5UL << 59)
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#define GITS_BASER_RaWaWt (6UL << 59)
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#define GITS_BASER_RaWaWb (7UL << 59)
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#define GITS_BASER_CACHEABILITY_MASK (7UL << 59)
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#define GITS_BASER_TYPE_SHIFT (56)
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#define GITS_BASER_VALID (1UL << 63)
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#define GITS_BASER_INDIRECT (1ULL << 62)
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#define GITS_BASER_INNER_CACHEABILITY_SHIFT (59)
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#define GITS_BASER_OUTER_CACHEABILITY_SHIFT (53)
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#define GITS_BASER_INNER_CACHEABILITY_MASK \
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GIC_BASER_CACHEABILITY(GITS_BASER, INNER, MASK)
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#define GITS_BASER_CACHEABILITY_MASK GITS_BASER_INNER_CACHEABILITY_MASK
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#define GITS_BASER_OUTER_CACHEABILITY_MASK \
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GIC_BASER_CACHEABILITY(GITS_BASER, OUTER, MASK)
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#define GITS_BASER_SHAREABILITY_MASK \
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GIC_BASER_SHAREABILITY(GITS_BASER, SHAREABILITY_MASK)
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#define GITS_BASER_nCnB GIC_BASER_CACHEABILITY(GITS_BASER, INNER, nCnB)
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#define GITS_BASER_nC GIC_BASER_CACHEABILITY(GITS_BASER, INNER, nC)
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#define GITS_BASER_RaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWt)
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#define GITS_BASER_RaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWt)
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#define GITS_BASER_WaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, WaWt)
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#define GITS_BASER_WaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, WaWb)
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#define GITS_BASER_RaWaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWaWt)
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#define GITS_BASER_RaWaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWaWb)
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#define GITS_BASER_TYPE_SHIFT (56)
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#define GITS_BASER_TYPE(r) (((r) >> GITS_BASER_TYPE_SHIFT) & 7)
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#define GITS_BASER_ENTRY_SIZE_SHIFT (48)
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#define GITS_BASER_ENTRY_SIZE_SHIFT (48)
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#define GITS_BASER_ENTRY_SIZE(r) ((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0xff) + 1)
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#define GITS_BASER_NonShareable (0UL << 10)
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#define GITS_BASER_InnerShareable (1UL << 10)
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#define GITS_BASER_OuterShareable (2UL << 10)
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#define GITS_BASER_SHAREABILITY_SHIFT (10)
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#define GITS_BASER_SHAREABILITY_MASK (3UL << GITS_BASER_SHAREABILITY_SHIFT)
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#define GITS_BASER_InnerShareable \
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GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable)
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#define GITS_BASER_PAGE_SIZE_SHIFT (8)
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#define GITS_BASER_PAGE_SIZE_4K (0UL << GITS_BASER_PAGE_SIZE_SHIFT)
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#define GITS_BASER_PAGE_SIZE_16K (1UL << GITS_BASER_PAGE_SIZE_SHIFT)
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@ -230,6 +301,7 @@
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#define GITS_BASER_PAGE_SIZE_MASK (3UL << GITS_BASER_PAGE_SIZE_SHIFT)
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#define GITS_BASER_PAGES_MAX 256
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#define GITS_BASER_PAGES_SHIFT (0)
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#define GITS_BASER_NR_PAGES(r) (((r) & 0xff) + 1)
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#define GITS_BASER_TYPE_NONE 0
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#define GITS_BASER_TYPE_DEVICE 1
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@ -247,7 +319,10 @@
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*/
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#define GITS_CMD_MAPD 0x08
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#define GITS_CMD_MAPC 0x09
|
||||
#define GITS_CMD_MAPVI 0x0a
|
||||
#define GITS_CMD_MAPTI 0x0a
|
||||
/* older GIC documentation used MAPVI for this command */
|
||||
#define GITS_CMD_MAPVI GITS_CMD_MAPTI
|
||||
#define GITS_CMD_MAPI 0x0b
|
||||
#define GITS_CMD_MOVI 0x01
|
||||
#define GITS_CMD_DISCARD 0x0f
|
||||
#define GITS_CMD_INV 0x0c
|
||||
|
|
@ -257,6 +332,22 @@
|
|||
#define GITS_CMD_CLEAR 0x04
|
||||
#define GITS_CMD_SYNC 0x05
|
||||
|
||||
/*
|
||||
* ITS error numbers
|
||||
*/
|
||||
#define E_ITS_MOVI_UNMAPPED_INTERRUPT 0x010107
|
||||
#define E_ITS_MOVI_UNMAPPED_COLLECTION 0x010109
|
||||
#define E_ITS_CLEAR_UNMAPPED_INTERRUPT 0x010507
|
||||
#define E_ITS_MAPD_DEVICE_OOR 0x010801
|
||||
#define E_ITS_MAPC_PROCNUM_OOR 0x010902
|
||||
#define E_ITS_MAPC_COLLECTION_OOR 0x010903
|
||||
#define E_ITS_MAPTI_UNMAPPED_DEVICE 0x010a04
|
||||
#define E_ITS_MAPTI_PHYSICALID_OOR 0x010a06
|
||||
#define E_ITS_INV_UNMAPPED_INTERRUPT 0x010c07
|
||||
#define E_ITS_INVALL_UNMAPPED_COLLECTION 0x010d09
|
||||
#define E_ITS_MOVALL_PROCNUM_OOR 0x010e01
|
||||
#define E_ITS_DISCARD_UNMAPPED_INTERRUPT 0x010f07
|
||||
|
||||
/*
|
||||
* CPU interface registers
|
||||
*/
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue