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drm/amdgpu/gmc9: add vega12 support (v2)

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Same as vega10.

v2: squash in golden regs fix from Feifei

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
This commit is contained in:
Alex Deucher 2018-03-13 20:25:08 -05:00
parent dca7b4015c
commit 273a14cd15
1 changed files with 4 additions and 0 deletions
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4
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
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@ -791,6 +791,7 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
if (amdgpu_gart_size == -1) { if (amdgpu_gart_size == -1) {
switch (adev->asic_type) { switch (adev->asic_type) {
case CHIP_VEGA10: /* all engines support GPUVM */ case CHIP_VEGA10: /* all engines support GPUVM */
case CHIP_VEGA12: /* all engines support GPUVM */
default: default:
adev->gmc.gart_size = 512ULL << 20; adev->gmc.gart_size = 512ULL << 20;
break; break;
@ -849,6 +850,7 @@ static int gmc_v9_0_sw_init(void *handle)
} }
break; break;
case CHIP_VEGA10: case CHIP_VEGA10:
case CHIP_VEGA12:
/* /*
* To fulfill 4-level page support, * To fulfill 4-level page support,
* vm size is 256TB (48bit), maximum size of Vega10, * vm size is 256TB (48bit), maximum size of Vega10,
@ -965,6 +967,8 @@ static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
golden_settings_athub_1_0_0, golden_settings_athub_1_0_0,
ARRAY_SIZE(golden_settings_athub_1_0_0)); ARRAY_SIZE(golden_settings_athub_1_0_0));
break; break;
case CHIP_VEGA12:
break;
case CHIP_RAVEN: case CHIP_RAVEN:
soc15_program_register_sequence(adev, soc15_program_register_sequence(adev,
golden_settings_athub_1_0_0, golden_settings_athub_1_0_0,