mirror of
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irqchip core changes for v3.18 (round 2)
- atmel
- Add sama5d4 support
- Correct # irqs for sama5d3
- broadcom
- Add bcm7120 l2 interrupt controller and DT binding
- gic-v3
- Add CPU PM notifier
- Add enable/disable support to gic_enable_redist
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Merge tag 'irqchip-core-3.18-2' of git://git.infradead.org/users/jcooper/linux into irq/core
irqchip core changes for v3.18 (round 2) from Jason Cooper
* atmel:
- Add sama5d4 support
- Correct # irqs for sama5d3
* broadcom:
- Add bcm7120 l2 interrupt controller and DT binding
* gic-v3:
- Add CPU PM notifier
- Add enable/disable support to gic_enable_redist
This commit is contained in:
Thomas Gleixner
commit
2828c9cdb8
6 changed files with 386 additions and 25 deletions
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@ -2,7 +2,7 @@
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Required properties:
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- compatible: Should be "atmel,<chip>-aic"
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<chip> can be "at91rm9200" or "sama5d3"
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<chip> can be "at91rm9200", "sama5d3" or "sama5d4"
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- interrupt-controller: Identifies the node as an interrupt controller.
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- interrupt-parent: For single AIC system, it is an empty property.
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- #interrupt-cells: The number of cells to define the interrupts. It should be 3.
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|
|
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@ -0,0 +1,86 @@
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Broadcom BCM7120-style Level 2 interrupt controller
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This interrupt controller hardware is a second level interrupt controller that
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is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
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platforms. It can be found on BCM7xxx products starting with BCM7120.
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Such an interrupt controller has the following hardware design:
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- outputs multiple interrupts signals towards its interrupt controller parent
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- controls how some of the interrupts will be flowing, whether they will
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directly output an interrupt signal towards the interrupt controller parent,
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or if they will output an interrupt signal at this 2nd level interrupt
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controller, in particular for UARTs
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- not all 32-bits within the interrupt controller actually map to an interrupt
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The typical hardware layout for this controller is represented below:
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2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC)
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0 -----[ MUX ] ------------|==========> GIC interrupt 75
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\-----------\
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1 -----[ MUX ] --------)---|==========> GIC interrupt 76
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\------------|
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2 -----[ MUX ] --------)---|==========> GIC interrupt 77
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\------------|
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3 ---------------------|
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4 ---------------------|
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5 ---------------------|
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7 ---------------------|---|===========> GIC interrupt 66
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9 ---------------------|
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10 --------------------|
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11 --------------------/
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6 ------------------------\
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|===========> GIC interrupt 64
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8 ------------------------/
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12 ........................ X
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13 ........................ X (not connected)
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..
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31 ........................ X
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Required properties:
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- compatible: should be "brcm,bcm7120-l2-intc"
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- reg: specifies the base physical address and size of the registers
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- interrupt-controller: identifies the node as an interrupt controller
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- #interrupt-cells: specifies the number of cells needed to encode an interrupt
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source, should be 1.
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- interrupt-parent: specifies the phandle to the parent interrupt controller
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this one is cascaded from
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- interrupts: specifies the interrupt line(s) in the interrupt-parent controller
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node, valid values depend on the type of parent interrupt controller
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- brcm,int-map-mask: 32-bits bit mask describing how many and which interrupts
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are wired to this 2nd level interrupt controller, and how they match their
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respective interrupt parents. Should match exactly the number of interrupts
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specified in the 'interrupts' property.
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Optional properties:
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- brcm,irq-can-wake: if present, this means the L2 controller can be used as a
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wakeup source for system suspend/resume.
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- brcm,int-fwd-mask: if present, a 32-bits bit mask to configure for the
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interrupts which have a mux gate, typically UARTs. Setting these bits will
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make their respective interrupts outputs bypass this 2nd level interrupt
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controller completely, it completely transparent for the interrupt controller
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parent
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Example:
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irq0_intc: interrupt-controller@f0406800 {
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compatible = "brcm,bcm7120-l2-intc";
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interrupt-parent = <&intc>;
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#interrupt-cells = <1>;
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reg = <0xf0406800 0x8>;
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interrupt-controller;
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interrupts = <0x0 0x42 0x0>, <0x0 0x40 0x0>;
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brcm,int-map-mask = <0xeb8>, <0x140>;
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brcm,int-fwd-mask = <0x7>;
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};
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@ -34,5 +34,6 @@ obj-$(CONFIG_TB10X_IRQC) += irq-tb10x.o
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obj-$(CONFIG_XTENSA) += irq-xtensa-pic.o
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obj-$(CONFIG_XTENSA_MX) += irq-xtensa-mx.o
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obj-$(CONFIG_IRQ_CROSSBAR) += irq-crossbar.o
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obj-$(CONFIG_BRCMSTB_L2_IRQ) += irq-brcmstb-l2.o
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obj-$(CONFIG_BRCMSTB_L2_IRQ) += irq-brcmstb-l2.o \
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irq-bcm7120-l2.o
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obj-$(CONFIG_KEYSTONE_IRQ) += irq-keystone.o
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@ -295,6 +295,7 @@ static void __init sama5d3_aic_irq_fixup(struct device_node *root)
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static const struct of_device_id __initdata aic5_irq_fixups[] = {
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{ .compatible = "atmel,sama5d3", .data = sama5d3_aic_irq_fixup },
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{ .compatible = "atmel,sama5d4", .data = sama5d3_aic_irq_fixup },
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{ /* sentinel */ },
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};
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@ -341,7 +342,7 @@ static int __init aic5_of_init(struct device_node *node,
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return 0;
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}
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#define NR_SAMA5D3_IRQS 50
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#define NR_SAMA5D3_IRQS 48
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static int __init sama5d3_aic5_of_init(struct device_node *node,
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struct device_node *parent)
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@ -349,3 +350,12 @@ static int __init sama5d3_aic5_of_init(struct device_node *node,
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return aic5_of_init(node, parent, NR_SAMA5D3_IRQS);
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}
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IRQCHIP_DECLARE(sama5d3_aic5, "atmel,sama5d3-aic", sama5d3_aic5_of_init);
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#define NR_SAMA5D4_IRQS 68
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static int __init sama5d4_aic5_of_init(struct device_node *node,
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struct device_node *parent)
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{
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return aic5_of_init(node, parent, NR_SAMA5D4_IRQS);
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}
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IRQCHIP_DECLARE(sama5d4_aic5, "atmel,sama5d4-aic", sama5d4_aic5_of_init);
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219
drivers/irqchip/irq-bcm7120-l2.c
Normal file
219
drivers/irqchip/irq-bcm7120-l2.c
Normal file
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@ -0,0 +1,219 @@
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/*
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* Broadcom BCM7120 style Level 2 interrupt controller driver
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*
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* Copyright (C) 2014 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/irqdomain.h>
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#include <linux/reboot.h>
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#include <linux/irqchip/chained_irq.h>
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#include "irqchip.h"
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#include <asm/mach/irq.h>
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/* Register offset in the L2 interrupt controller */
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#define IRQEN 0x00
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#define IRQSTAT 0x04
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struct bcm7120_l2_intc_data {
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void __iomem *base;
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struct irq_domain *domain;
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bool can_wake;
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u32 irq_fwd_mask;
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u32 irq_map_mask;
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u32 saved_mask;
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};
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static void bcm7120_l2_intc_irq_handle(unsigned int irq, struct irq_desc *desc)
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{
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struct bcm7120_l2_intc_data *b = irq_desc_get_handler_data(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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u32 status;
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chained_irq_enter(chip, desc);
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status = __raw_readl(b->base + IRQSTAT);
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if (status == 0) {
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do_bad_IRQ(irq, desc);
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goto out;
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}
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do {
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irq = ffs(status) - 1;
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status &= ~(1 << irq);
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generic_handle_irq(irq_find_mapping(b->domain, irq));
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} while (status);
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out:
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chained_irq_exit(chip, desc);
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}
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static void bcm7120_l2_intc_suspend(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct bcm7120_l2_intc_data *b = gc->private;
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u32 reg;
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irq_gc_lock(gc);
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/* Save the current mask and the interrupt forward mask */
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b->saved_mask = __raw_readl(b->base) | b->irq_fwd_mask;
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if (b->can_wake) {
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reg = b->saved_mask | gc->wake_active;
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__raw_writel(reg, b->base);
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}
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irq_gc_unlock(gc);
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}
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static void bcm7120_l2_intc_resume(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct bcm7120_l2_intc_data *b = gc->private;
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/* Restore the saved mask */
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irq_gc_lock(gc);
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__raw_writel(b->saved_mask, b->base);
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irq_gc_unlock(gc);
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}
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static int bcm7120_l2_intc_init_one(struct device_node *dn,
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struct bcm7120_l2_intc_data *data,
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int irq, const __be32 *map_mask)
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{
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int parent_irq;
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parent_irq = irq_of_parse_and_map(dn, irq);
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if (parent_irq < 0) {
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pr_err("failed to map interrupt %d\n", irq);
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return parent_irq;
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}
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data->irq_map_mask |= be32_to_cpup(map_mask + irq);
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irq_set_handler_data(parent_irq, data);
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irq_set_chained_handler(parent_irq, bcm7120_l2_intc_irq_handle);
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|
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return 0;
|
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}
|
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|
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int __init bcm7120_l2_intc_of_init(struct device_node *dn,
|
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struct device_node *parent)
|
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{
|
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unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
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struct bcm7120_l2_intc_data *data;
|
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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const __be32 *map_mask;
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int num_parent_irqs;
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int ret = 0, len, irq;
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|
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data = kzalloc(sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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|
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data->base = of_iomap(dn, 0);
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if (!data->base) {
|
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pr_err("failed to remap intc L2 registers\n");
|
||||
ret = -ENOMEM;
|
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goto out_free;
|
||||
}
|
||||
|
||||
if (of_property_read_u32(dn, "brcm,int-fwd-mask", &data->irq_fwd_mask))
|
||||
data->irq_fwd_mask = 0;
|
||||
|
||||
/* Enable all interrupt specified in the interrupt forward mask and have
|
||||
* the other disabled
|
||||
*/
|
||||
__raw_writel(data->irq_fwd_mask, data->base + IRQEN);
|
||||
|
||||
num_parent_irqs = of_irq_count(dn);
|
||||
if (num_parent_irqs <= 0) {
|
||||
pr_err("invalid number of parent interrupts\n");
|
||||
ret = -ENOMEM;
|
||||
goto out_unmap;
|
||||
}
|
||||
|
||||
map_mask = of_get_property(dn, "brcm,int-map-mask", &len);
|
||||
if (!map_mask || (len != (sizeof(*map_mask) * num_parent_irqs))) {
|
||||
pr_err("invalid brcm,int-map-mask property\n");
|
||||
ret = -EINVAL;
|
||||
goto out_unmap;
|
||||
}
|
||||
|
||||
for (irq = 0; irq < num_parent_irqs; irq++) {
|
||||
ret = bcm7120_l2_intc_init_one(dn, data, irq, map_mask);
|
||||
if (ret)
|
||||
goto out_unmap;
|
||||
}
|
||||
|
||||
data->domain = irq_domain_add_linear(dn, 32,
|
||||
&irq_generic_chip_ops, NULL);
|
||||
if (!data->domain) {
|
||||
ret = -ENOMEM;
|
||||
goto out_unmap;
|
||||
}
|
||||
|
||||
ret = irq_alloc_domain_generic_chips(data->domain, 32, 1,
|
||||
dn->full_name, handle_level_irq, clr, 0,
|
||||
IRQ_GC_INIT_MASK_CACHE);
|
||||
if (ret) {
|
||||
pr_err("failed to allocate generic irq chip\n");
|
||||
goto out_free_domain;
|
||||
}
|
||||
|
||||
gc = irq_get_domain_generic_chip(data->domain, 0);
|
||||
gc->unused = 0xfffffff & ~data->irq_map_mask;
|
||||
gc->reg_base = data->base;
|
||||
gc->private = data;
|
||||
ct = gc->chip_types;
|
||||
|
||||
ct->regs.mask = IRQEN;
|
||||
ct->chip.irq_mask = irq_gc_mask_clr_bit;
|
||||
ct->chip.irq_unmask = irq_gc_mask_set_bit;
|
||||
ct->chip.irq_ack = irq_gc_noop;
|
||||
ct->chip.irq_suspend = bcm7120_l2_intc_suspend;
|
||||
ct->chip.irq_resume = bcm7120_l2_intc_resume;
|
||||
|
||||
if (of_property_read_bool(dn, "brcm,irq-can-wake")) {
|
||||
data->can_wake = true;
|
||||
/* This IRQ chip can wake the system, set all relevant child
|
||||
* interupts in wake_enabled mask
|
||||
*/
|
||||
gc->wake_enabled = 0xffffffff;
|
||||
gc->wake_enabled &= ~gc->unused;
|
||||
ct->chip.irq_set_wake = irq_gc_set_wake;
|
||||
}
|
||||
|
||||
pr_info("registered BCM7120 L2 intc (mem: 0x%p, parent IRQ(s): %d)\n",
|
||||
data->base, num_parent_irqs);
|
||||
|
||||
return 0;
|
||||
|
||||
out_free_domain:
|
||||
irq_domain_remove(data->domain);
|
||||
out_unmap:
|
||||
iounmap(data->base);
|
||||
out_free:
|
||||
kfree(data);
|
||||
return ret;
|
||||
}
|
||||
IRQCHIP_DECLARE(brcmstb_l2_intc, "brcm,bcm7120-l2-intc",
|
||||
bcm7120_l2_intc_of_init);
|
||||
|
|
@ -16,6 +16,7 @@
|
|||
*/
|
||||
|
||||
#include <linux/cpu.h>
|
||||
#include <linux/cpu_pm.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/of.h>
|
||||
|
|
@ -155,7 +156,7 @@ static void gic_enable_sre(void)
|
|||
pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n");
|
||||
}
|
||||
|
||||
static void gic_enable_redist(void)
|
||||
static void gic_enable_redist(bool enable)
|
||||
{
|
||||
void __iomem *rbase;
|
||||
u32 count = 1000000; /* 1s! */
|
||||
|
|
@ -163,20 +164,30 @@ static void gic_enable_redist(void)
|
|||
|
||||
rbase = gic_data_rdist_rd_base();
|
||||
|
||||
/* Wake up this CPU redistributor */
|
||||
val = readl_relaxed(rbase + GICR_WAKER);
|
||||
val &= ~GICR_WAKER_ProcessorSleep;
|
||||
if (enable)
|
||||
/* Wake up this CPU redistributor */
|
||||
val &= ~GICR_WAKER_ProcessorSleep;
|
||||
else
|
||||
val |= GICR_WAKER_ProcessorSleep;
|
||||
writel_relaxed(val, rbase + GICR_WAKER);
|
||||
|
||||
while (readl_relaxed(rbase + GICR_WAKER) & GICR_WAKER_ChildrenAsleep) {
|
||||
count--;
|
||||
if (!count) {
|
||||
pr_err_ratelimited("redist didn't wake up...\n");
|
||||
return;
|
||||
}
|
||||
if (!enable) { /* Check that GICR_WAKER is writeable */
|
||||
val = readl_relaxed(rbase + GICR_WAKER);
|
||||
if (!(val & GICR_WAKER_ProcessorSleep))
|
||||
return; /* No PM support in this redistributor */
|
||||
}
|
||||
|
||||
while (count--) {
|
||||
val = readl_relaxed(rbase + GICR_WAKER);
|
||||
if (enable ^ (val & GICR_WAKER_ChildrenAsleep))
|
||||
break;
|
||||
cpu_relax();
|
||||
udelay(1);
|
||||
};
|
||||
if (!count)
|
||||
pr_err_ratelimited("redistributor failed to %s...\n",
|
||||
enable ? "wakeup" : "sleep");
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -372,20 +383,8 @@ static int gic_populate_rdist(void)
|
|||
return -ENODEV;
|
||||
}
|
||||
|
||||
static void gic_cpu_init(void)
|
||||
static void gic_cpu_sys_reg_init(void)
|
||||
{
|
||||
void __iomem *rbase;
|
||||
|
||||
/* Register ourselves with the rest of the world */
|
||||
if (gic_populate_rdist())
|
||||
return;
|
||||
|
||||
gic_enable_redist();
|
||||
|
||||
rbase = gic_data_rdist_sgi_base();
|
||||
|
||||
gic_cpu_config(rbase, gic_redist_wait_for_rwp);
|
||||
|
||||
/* Enable system registers */
|
||||
gic_enable_sre();
|
||||
|
||||
|
|
@ -399,6 +398,24 @@ static void gic_cpu_init(void)
|
|||
gic_write_grpen1(1);
|
||||
}
|
||||
|
||||
static void gic_cpu_init(void)
|
||||
{
|
||||
void __iomem *rbase;
|
||||
|
||||
/* Register ourselves with the rest of the world */
|
||||
if (gic_populate_rdist())
|
||||
return;
|
||||
|
||||
gic_enable_redist(true);
|
||||
|
||||
rbase = gic_data_rdist_sgi_base();
|
||||
|
||||
gic_cpu_config(rbase, gic_redist_wait_for_rwp);
|
||||
|
||||
/* initialise system registers */
|
||||
gic_cpu_sys_reg_init();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
static int gic_secondary_init(struct notifier_block *nfb,
|
||||
unsigned long action, void *hcpu)
|
||||
|
|
@ -532,6 +549,33 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
|
|||
#define gic_smp_init() do { } while(0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CPU_PM
|
||||
static int gic_cpu_pm_notifier(struct notifier_block *self,
|
||||
unsigned long cmd, void *v)
|
||||
{
|
||||
if (cmd == CPU_PM_EXIT) {
|
||||
gic_enable_redist(true);
|
||||
gic_cpu_sys_reg_init();
|
||||
} else if (cmd == CPU_PM_ENTER) {
|
||||
gic_write_grpen1(0);
|
||||
gic_enable_redist(false);
|
||||
}
|
||||
return NOTIFY_OK;
|
||||
}
|
||||
|
||||
static struct notifier_block gic_cpu_pm_notifier_block = {
|
||||
.notifier_call = gic_cpu_pm_notifier,
|
||||
};
|
||||
|
||||
static void gic_cpu_pm_init(void)
|
||||
{
|
||||
cpu_pm_register_notifier(&gic_cpu_pm_notifier_block);
|
||||
}
|
||||
|
||||
#else
|
||||
static inline void gic_cpu_pm_init(void) { }
|
||||
#endif /* CONFIG_CPU_PM */
|
||||
|
||||
static struct irq_chip gic_chip = {
|
||||
.name = "GICv3",
|
||||
.irq_mask = gic_mask_irq,
|
||||
|
|
@ -671,6 +715,7 @@ static int __init gic_of_init(struct device_node *node, struct device_node *pare
|
|||
gic_smp_init();
|
||||
gic_dist_init();
|
||||
gic_cpu_init();
|
||||
gic_cpu_pm_init();
|
||||
|
||||
return 0;
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue