mirror of
https://github.com/Fishwaldo/linux-bl808.git
synced 2025-06-17 20:25:19 +00:00
ARM: SoC drivers for v5.11
There are a couple of subsystems maintained by other people that
merge their drivers through the SoC tree, those changes include:
- The SCMI firmware framework gains support for sensor notifications
and for controlling voltage domains.
- A large update for the Tegra memory controller driver, integrating
it better with the interconnect framework
- The memory controller subsystem gains support for Mediatek MT8192
- The reset controller framework gains support for sharing pulsed
resets
For Soc specific drivers in drivers/soc, the main changes are
- The Allwinner/sunxi MBUS gets a rework for the way it handles
dma_map_ops and offsets between physical and dma address spaces.
- An errata fix plus some cleanups for Freescale Layerscape SoCs
- A cleanup for renesas drivers regarding MMIO accesses.
- New SoC specific drivers for Mediatek MT8192 and MT8183 power domains
- New SoC specific drivers for Aspeed AST2600 LPC bus control
and SoC identification.
- Core Power Domain support for Qualcomm MSM8916, MSM8939, SDM660
and SDX55.
- A rework of the TI AM33xx 'genpd' power domain support to use
information from DT instead of platform data
- Support for TI AM64x SoCs
- Allow building some Amlogic drivers as modules instead of built-in
Finally, there are numerous cleanups and smaller bug fixes for
Mediatek, Tegra, Samsung, Qualcomm, TI OMAP, Amlogic, Rockchips,
Renesas, and Xilinx SoCs.
There is a trivial conflict in the cedrus driver, with two branches
adding the same CEDRUS_CAPABILITY_H265_DEC flag, and another trivial
remove/remove conflict in linux/dma-mapping.h.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Merge tag 'arm-soc-drivers-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC driver updates from Arnd Bergmann:
"There are a couple of subsystems maintained by other people that merge
their drivers through the SoC tree, those changes include:
- The SCMI firmware framework gains support for sensor notifications
and for controlling voltage domains.
- A large update for the Tegra memory controller driver, integrating
it better with the interconnect framework
- The memory controller subsystem gains support for Mediatek MT8192
- The reset controller framework gains support for sharing pulsed
resets
For Soc specific drivers in drivers/soc, the main changes are
- The Allwinner/sunxi MBUS gets a rework for the way it handles
dma_map_ops and offsets between physical and dma address spaces.
- An errata fix plus some cleanups for Freescale Layerscape SoCs
- A cleanup for renesas drivers regarding MMIO accesses.
- New SoC specific drivers for Mediatek MT8192 and MT8183 power
domains
- New SoC specific drivers for Aspeed AST2600 LPC bus control and SoC
identification.
- Core Power Domain support for Qualcomm MSM8916, MSM8939, SDM660 and
SDX55.
- A rework of the TI AM33xx 'genpd' power domain support to use
information from DT instead of platform data
- Support for TI AM64x SoCs
- Allow building some Amlogic drivers as modules instead of built-in
Finally, there are numerous cleanups and smaller bug fixes for
Mediatek, Tegra, Samsung, Qualcomm, TI OMAP, Amlogic, Rockchips,
Renesas, and Xilinx SoCs"
* tag 'arm-soc-drivers-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (222 commits)
soc: mediatek: mmsys: Specify HAS_IOMEM dependency for MTK_MMSYS
firmware: xilinx: Properly align function parameter
firmware: xilinx: Add a blank line after function declaration
firmware: xilinx: Remove additional newline
firmware: xilinx: Fix kernel-doc warnings
firmware: xlnx-zynqmp: fix compilation warning
soc: xilinx: vcu: add missing register NUM_CORE
soc: xilinx: vcu: use vcu-settings syscon registers
dt-bindings: soc: xlnx: extract xlnx, vcu-settings to separate binding
soc: xilinx: vcu: drop useless success message
clk: samsung: mark PM functions as __maybe_unused
soc: samsung: exynos-chipid: initialize later - with arch_initcall
soc: samsung: exynos-chipid: order list of SoCs by name
memory: jz4780_nemc: Fix potential NULL dereference in jz4780_nemc_probe()
memory: ti-emif-sram: only build for ARMv7
memory: tegra30: Support interconnect framework
memory: tegra20: Support hardware versioning and clean up OPP table initialization
dt-bindings: memory: tegra20-emc: Document opp-supported-hw property
soc: rockchip: io-domain: Fix error return code in rockchip_iodomain_probe()
reset-controller: ti: force the write operation when assert or deassert
...
This commit is contained in:
Linus Torvalds
commit
48c1c40ab4
182 changed files with 6621 additions and 1357 deletions
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@ -55,6 +55,9 @@ static inline void *imx_dsp_get_data(struct imx_dsp_ipc *ipc)
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int imx_dsp_ring_doorbell(struct imx_dsp_ipc *dsp, unsigned int chan_idx);
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struct mbox_chan *imx_dsp_request_channel(struct imx_dsp_ipc *ipc, int idx);
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void imx_dsp_free_channel(struct imx_dsp_ipc *ipc, int idx);
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#else
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static inline int imx_dsp_ring_doorbell(struct imx_dsp_ipc *ipc,
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@ -63,5 +66,12 @@ static inline int imx_dsp_ring_doorbell(struct imx_dsp_ipc *ipc,
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return -ENOTSUPP;
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}
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struct mbox_chan *imx_dsp_request_channel(struct imx_dsp_ipc *ipc, int idx)
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{
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return ERR_PTR(-EOPNOTSUPP);
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}
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void imx_dsp_free_channel(struct imx_dsp_ipc *ipc, int idx) { }
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#endif
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#endif /* _IMX_DSP_IPC_H */
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@ -34,6 +34,7 @@ struct imx_sc_rpc_msg {
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uint8_t func;
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};
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#ifdef CONFIG_IMX_SCU
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/*
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* This is an function to send an RPC message over an IPC channel.
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* It is called by client-side SCFW API function shims.
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@ -55,4 +56,16 @@ int imx_scu_call_rpc(struct imx_sc_ipc *ipc, void *msg, bool have_resp);
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* @return Returns an error code (0 = success, failed if < 0)
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*/
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int imx_scu_get_handle(struct imx_sc_ipc **ipc);
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#else
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static inline int imx_scu_call_rpc(struct imx_sc_ipc *ipc, void *msg,
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bool have_resp)
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{
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return -ENOTSUPP;
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}
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static inline int imx_scu_get_handle(struct imx_sc_ipc **ipc)
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{
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return -ENOTSUPP;
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}
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#endif
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#endif /* _SC_IPC_H */
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@ -16,9 +16,36 @@
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#include <linux/firmware/imx/svc/pm.h>
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#include <linux/firmware/imx/svc/rm.h>
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#if IS_ENABLED(CONFIG_IMX_SCU)
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int imx_scu_enable_general_irq_channel(struct device *dev);
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int imx_scu_irq_register_notifier(struct notifier_block *nb);
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int imx_scu_irq_unregister_notifier(struct notifier_block *nb);
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int imx_scu_irq_group_enable(u8 group, u32 mask, u8 enable);
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int imx_scu_soc_init(struct device *dev);
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#else
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static inline int imx_scu_soc_init(struct device *dev)
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{
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return -ENOTSUPP;
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}
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static inline int imx_scu_enable_general_irq_channel(struct device *dev)
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{
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return -ENOTSUPP;
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}
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static inline int imx_scu_irq_register_notifier(struct notifier_block *nb)
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{
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return -ENOTSUPP;
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}
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static inline int imx_scu_irq_unregister_notifier(struct notifier_block *nb)
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{
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return -ENOTSUPP;
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}
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static inline int imx_scu_irq_group_enable(u8 group, u32 mask, u8 enable)
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{
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return -ENOTSUPP;
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}
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#endif
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#endif /* _SC_SCI_H */
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@ -46,6 +46,7 @@ enum imx_misc_func {
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* Control Functions
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*/
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#ifdef CONFIG_IMX_SCU
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int imx_sc_misc_set_control(struct imx_sc_ipc *ipc, u32 resource,
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u8 ctrl, u32 val);
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@ -54,5 +55,23 @@ int imx_sc_misc_get_control(struct imx_sc_ipc *ipc, u32 resource,
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int imx_sc_pm_cpu_start(struct imx_sc_ipc *ipc, u32 resource,
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bool enable, u64 phys_addr);
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#else
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static inline int imx_sc_misc_set_control(struct imx_sc_ipc *ipc,
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u32 resource, u8 ctrl, u32 val)
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{
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return -ENOTSUPP;
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}
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static inline int imx_sc_misc_get_control(struct imx_sc_ipc *ipc,
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u32 resource, u8 ctrl, u32 *val)
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{
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return -ENOTSUPP;
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}
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static inline int imx_sc_pm_cpu_start(struct imx_sc_ipc *ipc, u32 resource,
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bool enable, u64 phys_addr)
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{
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return -ENOTSUPP;
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}
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#endif
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#endif /* _SC_MISC_API_H */
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@ -13,6 +13,8 @@
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#ifndef __FIRMWARE_ZYNQMP_H__
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#define __FIRMWARE_ZYNQMP_H__
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#include <linux/err.h>
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#define ZYNQMP_PM_VERSION_MAJOR 1
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#define ZYNQMP_PM_VERSION_MINOR 0
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@ -310,7 +312,6 @@ struct zynqmp_pm_query_data {
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u32 arg3;
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};
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int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1,
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u32 arg2, u32 arg3, u32 *ret_payload);
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@ -358,147 +359,181 @@ static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void)
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{
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return ERR_PTR(-ENODEV);
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}
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static inline int zynqmp_pm_get_api_version(u32 *version)
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{
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return -ENODEV;
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}
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static inline int zynqmp_pm_get_chipid(u32 *idcode, u32 *version)
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{
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return -ENODEV;
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}
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static inline int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata,
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u32 *out)
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{
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return -ENODEV;
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}
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static inline int zynqmp_pm_clock_enable(u32 clock_id)
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{
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return -ENODEV;
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}
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static inline int zynqmp_pm_clock_disable(u32 clock_id)
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{
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return -ENODEV;
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}
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static inline int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state)
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{
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return -ENODEV;
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}
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static inline int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider)
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{
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return -ENODEV;
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}
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static inline int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider)
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{
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return -ENODEV;
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}
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static inline int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate)
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{
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return -ENODEV;
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}
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static inline int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate)
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{
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return -ENODEV;
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}
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static inline int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id)
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{
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return -ENODEV;
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}
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static inline int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id)
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{
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return -ENODEV;
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}
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static inline int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode)
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{
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return -ENODEV;
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}
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static inline int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode)
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{
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return -ENODEV;
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}
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static inline int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data)
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{
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return -ENODEV;
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}
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static inline int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data)
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{
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return -ENODEV;
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}
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static inline int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value)
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{
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return -ENODEV;
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}
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static inline int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type)
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{
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return -ENODEV;
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}
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static inline int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,
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const enum zynqmp_pm_reset_action assert_flag)
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const enum zynqmp_pm_reset_action assert_flag)
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{
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return -ENODEV;
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}
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static inline int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset,
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u32 *status)
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{
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return -ENODEV;
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}
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static inline int zynqmp_pm_init_finalize(void)
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{
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return -ENODEV;
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}
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static inline int zynqmp_pm_set_suspend_mode(u32 mode)
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{
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return -ENODEV;
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}
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static inline int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
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const u32 qos,
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const enum zynqmp_pm_request_ack ack)
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{
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return -ENODEV;
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}
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static inline int zynqmp_pm_release_node(const u32 node)
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{
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return -ENODEV;
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}
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static inline int zynqmp_pm_set_requirement(const u32 node,
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const u32 capabilities,
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const u32 qos,
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const enum zynqmp_pm_request_ack ack)
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const u32 capabilities,
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const u32 qos,
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const enum zynqmp_pm_request_ack ack)
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{
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return -ENODEV;
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}
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static inline int zynqmp_pm_aes_engine(const u64 address, u32 *out)
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{
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return -ENODEV;
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}
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static inline int zynqmp_pm_fpga_load(const u64 address, const u32 size,
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const u32 flags)
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{
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return -ENODEV;
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}
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static inline int zynqmp_pm_fpga_get_status(u32 *value)
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{
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return -ENODEV;
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}
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static inline int zynqmp_pm_write_ggs(u32 index, u32 value)
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{
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return -ENODEV;
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}
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static inline int zynqmp_pm_read_ggs(u32 index, u32 *value)
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{
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return -ENODEV;
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}
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static inline int zynqmp_pm_write_pggs(u32 index, u32 value)
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{
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return -ENODEV;
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}
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static inline int zynqmp_pm_read_pggs(u32 index, u32 *value)
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{
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return -ENODEV;
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}
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static inline int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype)
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{
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return -ENODEV;
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}
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static inline int zynqmp_pm_set_boot_health_status(u32 value)
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{
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return -ENODEV;
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Loading…
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Add a link
Reference in a new issue