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sh: clkfwk: Support variable size accesses for MSTP clocks.
The bulk of the MSTP users require 32-bit access, but this isn't the case for some of the SH-2A parts, so add in some basic infrastructure to let the CPU define its required access size in preparation. Requested-by: Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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2 changed files with 58 additions and 14 deletions
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@ -59,7 +59,15 @@ struct clk {
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unsigned int nr_freqs;
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};
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#define CLK_ENABLE_ON_INIT (1 << 0)
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#define CLK_ENABLE_ON_INIT BIT(0)
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#define CLK_ENABLE_REG_32BIT BIT(1) /* default access size */
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#define CLK_ENABLE_REG_16BIT BIT(2)
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#define CLK_ENABLE_REG_8BIT BIT(3)
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#define CLK_ENABLE_REG_MASK (CLK_ENABLE_REG_32BIT | \
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CLK_ENABLE_REG_16BIT | \
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CLK_ENABLE_REG_8BIT)
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/* drivers/sh/clk.c */
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unsigned long followparent_recalc(struct clk *);
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@ -102,7 +110,7 @@ long clk_round_parent(struct clk *clk, unsigned long target,
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unsigned long *best_freq, unsigned long *parent_freq,
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unsigned int div_min, unsigned int div_max);
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#define SH_CLK_MSTP32(_parent, _enable_reg, _enable_bit, _flags) \
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#define SH_CLK_MSTP(_parent, _enable_reg, _enable_bit, _flags) \
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{ \
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.parent = _parent, \
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.enable_reg = (void __iomem *)_enable_reg, \
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@ -110,7 +118,27 @@ long clk_round_parent(struct clk *clk, unsigned long target,
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.flags = _flags, \
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}
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int sh_clk_mstp32_register(struct clk *clks, int nr);
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#define SH_CLK_MSTP32(_p, _r, _b, _f) \
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SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_32BIT)
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#define SH_CLK_MSTP16(_p, _r, _b, _f) \
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SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_16BIT)
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#define SH_CLK_MSTP8(_p, _r, _b, _f) \
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SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_8BIT)
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int sh_clk_mstp_register(struct clk *clks, int nr);
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/*
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* MSTP registration never really cared about access size, despite the
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* original enable/disable pairs assuming a 32-bit access. Clocks are
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* responsible for defining their access sizes either directly or via the
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* clock definition wrappers.
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*/
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static inline int __deprecated sh_clk_mstp32_register(struct clk *clks, int nr)
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{
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return sh_clk_mstp_register(clks, nr);
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}
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#define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \
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{ \
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