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https://github.com/Fishwaldo/linux-bl808.git
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ice: Add additional CSR registers to ETHTOOL_GREGS
In the event of a Tx hang it can be useful to read a variety of hardware registers to capture some state about why the transmit queue got stuck. Extend the ETHTOOL_GREGS dump provided by the ice driver with several CSR registers that provide such relevant information regarding the hardware Tx state. This enables capturing relevant data to enable debugging such a Tx hang. Signed-off-by: Lukasz Czapnik <lukasz.czapnik@intel.com> Signed-off-by: Mateusz Palczewski <mateusz.palczewski@intel.com> Tested-by: Gurucharan <gurucharanx.g@intel.com> (A Contingent worker at Intel) Link: https://lore.kernel.org/r/20221027104239.1691549-1-jacob.e.keller@intel.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Lukasz Czapnik
Jakub Kicinski
parent
006436316f
commit
637639cbfe
1 changed files with 169 additions and 0 deletions
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@ -151,6 +151,175 @@ static const u32 ice_regs_dump_list[] = {
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QINT_RQCTL(0),
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PFINT_OICR_ENA,
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QRX_ITR(0),
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#define GLDCB_TLPM_PCI_DM 0x000A0180
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GLDCB_TLPM_PCI_DM,
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#define GLDCB_TLPM_TC2PFC 0x000A0194
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GLDCB_TLPM_TC2PFC,
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#define TCDCB_TLPM_WAIT_DM(_i) (0x000A0080 + ((_i) * 4))
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TCDCB_TLPM_WAIT_DM(0),
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TCDCB_TLPM_WAIT_DM(1),
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TCDCB_TLPM_WAIT_DM(2),
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TCDCB_TLPM_WAIT_DM(3),
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TCDCB_TLPM_WAIT_DM(4),
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TCDCB_TLPM_WAIT_DM(5),
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TCDCB_TLPM_WAIT_DM(6),
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TCDCB_TLPM_WAIT_DM(7),
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TCDCB_TLPM_WAIT_DM(8),
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TCDCB_TLPM_WAIT_DM(9),
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TCDCB_TLPM_WAIT_DM(10),
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TCDCB_TLPM_WAIT_DM(11),
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TCDCB_TLPM_WAIT_DM(12),
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TCDCB_TLPM_WAIT_DM(13),
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TCDCB_TLPM_WAIT_DM(14),
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TCDCB_TLPM_WAIT_DM(15),
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TCDCB_TLPM_WAIT_DM(16),
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TCDCB_TLPM_WAIT_DM(17),
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TCDCB_TLPM_WAIT_DM(18),
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TCDCB_TLPM_WAIT_DM(19),
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TCDCB_TLPM_WAIT_DM(20),
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TCDCB_TLPM_WAIT_DM(21),
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TCDCB_TLPM_WAIT_DM(22),
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TCDCB_TLPM_WAIT_DM(23),
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TCDCB_TLPM_WAIT_DM(24),
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TCDCB_TLPM_WAIT_DM(25),
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TCDCB_TLPM_WAIT_DM(26),
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TCDCB_TLPM_WAIT_DM(27),
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TCDCB_TLPM_WAIT_DM(28),
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TCDCB_TLPM_WAIT_DM(29),
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TCDCB_TLPM_WAIT_DM(30),
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TCDCB_TLPM_WAIT_DM(31),
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#define GLPCI_WATMK_CLNT_PIPEMON 0x000BFD90
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GLPCI_WATMK_CLNT_PIPEMON,
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#define GLPCI_CUR_CLNT_COMMON 0x000BFD84
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GLPCI_CUR_CLNT_COMMON,
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#define GLPCI_CUR_CLNT_PIPEMON 0x000BFD88
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GLPCI_CUR_CLNT_PIPEMON,
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#define GLPCI_PCIERR 0x0009DEB0
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GLPCI_PCIERR,
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#define GLPSM_DEBUG_CTL_STATUS 0x000B0600
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GLPSM_DEBUG_CTL_STATUS,
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#define GLPSM0_DEBUG_FIFO_OVERFLOW_DETECT 0x000B0680
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GLPSM0_DEBUG_FIFO_OVERFLOW_DETECT,
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#define GLPSM0_DEBUG_FIFO_UNDERFLOW_DETECT 0x000B0684
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GLPSM0_DEBUG_FIFO_UNDERFLOW_DETECT,
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#define GLPSM0_DEBUG_DT_OUT_OF_WINDOW 0x000B0688
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GLPSM0_DEBUG_DT_OUT_OF_WINDOW,
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#define GLPSM0_DEBUG_INTF_HW_ERROR_DETECT 0x000B069C
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GLPSM0_DEBUG_INTF_HW_ERROR_DETECT,
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#define GLPSM0_DEBUG_MISC_HW_ERROR_DETECT 0x000B06A0
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GLPSM0_DEBUG_MISC_HW_ERROR_DETECT,
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#define GLPSM1_DEBUG_FIFO_OVERFLOW_DETECT 0x000B0E80
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GLPSM1_DEBUG_FIFO_OVERFLOW_DETECT,
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#define GLPSM1_DEBUG_FIFO_UNDERFLOW_DETECT 0x000B0E84
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GLPSM1_DEBUG_FIFO_UNDERFLOW_DETECT,
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#define GLPSM1_DEBUG_SRL_FIFO_OVERFLOW_DETECT 0x000B0E88
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GLPSM1_DEBUG_SRL_FIFO_OVERFLOW_DETECT,
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#define GLPSM1_DEBUG_SRL_FIFO_UNDERFLOW_DETECT 0x000B0E8C
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GLPSM1_DEBUG_SRL_FIFO_UNDERFLOW_DETECT,
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#define GLPSM1_DEBUG_MISC_HW_ERROR_DETECT 0x000B0E90
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GLPSM1_DEBUG_MISC_HW_ERROR_DETECT,
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#define GLPSM2_DEBUG_FIFO_OVERFLOW_DETECT 0x000B1680
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GLPSM2_DEBUG_FIFO_OVERFLOW_DETECT,
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#define GLPSM2_DEBUG_FIFO_UNDERFLOW_DETECT 0x000B1684
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GLPSM2_DEBUG_FIFO_UNDERFLOW_DETECT,
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#define GLPSM2_DEBUG_MISC_HW_ERROR_DETECT 0x000B1688
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GLPSM2_DEBUG_MISC_HW_ERROR_DETECT,
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#define GLTDPU_TCLAN_COMP_BOB(_i) (0x00049ADC + ((_i) * 4))
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GLTDPU_TCLAN_COMP_BOB(1),
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GLTDPU_TCLAN_COMP_BOB(2),
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GLTDPU_TCLAN_COMP_BOB(3),
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GLTDPU_TCLAN_COMP_BOB(4),
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GLTDPU_TCLAN_COMP_BOB(5),
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GLTDPU_TCLAN_COMP_BOB(6),
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GLTDPU_TCLAN_COMP_BOB(7),
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GLTDPU_TCLAN_COMP_BOB(8),
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#define GLTDPU_TCB_CMD_BOB(_i) (0x0004975C + ((_i) * 4))
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GLTDPU_TCB_CMD_BOB(1),
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GLTDPU_TCB_CMD_BOB(2),
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GLTDPU_TCB_CMD_BOB(3),
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GLTDPU_TCB_CMD_BOB(4),
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GLTDPU_TCB_CMD_BOB(5),
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GLTDPU_TCB_CMD_BOB(6),
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GLTDPU_TCB_CMD_BOB(7),
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GLTDPU_TCB_CMD_BOB(8),
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#define GLTDPU_PSM_UPDATE_BOB(_i) (0x00049B5C + ((_i) * 4))
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GLTDPU_PSM_UPDATE_BOB(1),
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GLTDPU_PSM_UPDATE_BOB(2),
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GLTDPU_PSM_UPDATE_BOB(3),
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GLTDPU_PSM_UPDATE_BOB(4),
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GLTDPU_PSM_UPDATE_BOB(5),
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GLTDPU_PSM_UPDATE_BOB(6),
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GLTDPU_PSM_UPDATE_BOB(7),
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GLTDPU_PSM_UPDATE_BOB(8),
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#define GLTCB_CMD_IN_BOB(_i) (0x000AE288 + ((_i) * 4))
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GLTCB_CMD_IN_BOB(1),
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GLTCB_CMD_IN_BOB(2),
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GLTCB_CMD_IN_BOB(3),
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GLTCB_CMD_IN_BOB(4),
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GLTCB_CMD_IN_BOB(5),
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GLTCB_CMD_IN_BOB(6),
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GLTCB_CMD_IN_BOB(7),
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GLTCB_CMD_IN_BOB(8),
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#define GLLAN_TCLAN_FETCH_CTL_FBK_BOB_CTL(_i) (0x000FC148 + ((_i) * 4))
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GLLAN_TCLAN_FETCH_CTL_FBK_BOB_CTL(1),
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GLLAN_TCLAN_FETCH_CTL_FBK_BOB_CTL(2),
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GLLAN_TCLAN_FETCH_CTL_FBK_BOB_CTL(3),
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GLLAN_TCLAN_FETCH_CTL_FBK_BOB_CTL(4),
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GLLAN_TCLAN_FETCH_CTL_FBK_BOB_CTL(5),
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GLLAN_TCLAN_FETCH_CTL_FBK_BOB_CTL(6),
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GLLAN_TCLAN_FETCH_CTL_FBK_BOB_CTL(7),
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GLLAN_TCLAN_FETCH_CTL_FBK_BOB_CTL(8),
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#define GLLAN_TCLAN_FETCH_CTL_SCHED_BOB_CTL(_i) (0x000FC248 + ((_i) * 4))
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GLLAN_TCLAN_FETCH_CTL_SCHED_BOB_CTL(1),
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GLLAN_TCLAN_FETCH_CTL_SCHED_BOB_CTL(2),
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GLLAN_TCLAN_FETCH_CTL_SCHED_BOB_CTL(3),
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GLLAN_TCLAN_FETCH_CTL_SCHED_BOB_CTL(4),
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GLLAN_TCLAN_FETCH_CTL_SCHED_BOB_CTL(5),
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GLLAN_TCLAN_FETCH_CTL_SCHED_BOB_CTL(6),
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GLLAN_TCLAN_FETCH_CTL_SCHED_BOB_CTL(7),
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GLLAN_TCLAN_FETCH_CTL_SCHED_BOB_CTL(8),
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#define GLLAN_TCLAN_CACHE_CTL_BOB_CTL(_i) (0x000FC1C8 + ((_i) * 4))
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GLLAN_TCLAN_CACHE_CTL_BOB_CTL(1),
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GLLAN_TCLAN_CACHE_CTL_BOB_CTL(2),
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GLLAN_TCLAN_CACHE_CTL_BOB_CTL(3),
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GLLAN_TCLAN_CACHE_CTL_BOB_CTL(4),
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GLLAN_TCLAN_CACHE_CTL_BOB_CTL(5),
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GLLAN_TCLAN_CACHE_CTL_BOB_CTL(6),
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GLLAN_TCLAN_CACHE_CTL_BOB_CTL(7),
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GLLAN_TCLAN_CACHE_CTL_BOB_CTL(8),
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#define GLLAN_TCLAN_FETCH_CTL_PROC_BOB_CTL(_i) (0x000FC188 + ((_i) * 4))
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GLLAN_TCLAN_FETCH_CTL_PROC_BOB_CTL(1),
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GLLAN_TCLAN_FETCH_CTL_PROC_BOB_CTL(2),
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GLLAN_TCLAN_FETCH_CTL_PROC_BOB_CTL(3),
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GLLAN_TCLAN_FETCH_CTL_PROC_BOB_CTL(4),
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GLLAN_TCLAN_FETCH_CTL_PROC_BOB_CTL(5),
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GLLAN_TCLAN_FETCH_CTL_PROC_BOB_CTL(6),
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GLLAN_TCLAN_FETCH_CTL_PROC_BOB_CTL(7),
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GLLAN_TCLAN_FETCH_CTL_PROC_BOB_CTL(8),
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#define GLLAN_TCLAN_FETCH_CTL_PCIE_RD_BOB_CTL(_i) (0x000FC288 + ((_i) * 4))
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GLLAN_TCLAN_FETCH_CTL_PCIE_RD_BOB_CTL(1),
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GLLAN_TCLAN_FETCH_CTL_PCIE_RD_BOB_CTL(2),
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GLLAN_TCLAN_FETCH_CTL_PCIE_RD_BOB_CTL(3),
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GLLAN_TCLAN_FETCH_CTL_PCIE_RD_BOB_CTL(4),
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GLLAN_TCLAN_FETCH_CTL_PCIE_RD_BOB_CTL(5),
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GLLAN_TCLAN_FETCH_CTL_PCIE_RD_BOB_CTL(6),
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GLLAN_TCLAN_FETCH_CTL_PCIE_RD_BOB_CTL(7),
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GLLAN_TCLAN_FETCH_CTL_PCIE_RD_BOB_CTL(8),
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#define PRTDCB_TCUPM_REG_CM(_i) (0x000BC360 + ((_i) * 4))
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PRTDCB_TCUPM_REG_CM(0),
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PRTDCB_TCUPM_REG_CM(1),
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PRTDCB_TCUPM_REG_CM(2),
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PRTDCB_TCUPM_REG_CM(3),
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#define PRTDCB_TCUPM_REG_DM(_i) (0x000BC3A0 + ((_i) * 4))
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PRTDCB_TCUPM_REG_DM(0),
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PRTDCB_TCUPM_REG_DM(1),
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PRTDCB_TCUPM_REG_DM(2),
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PRTDCB_TCUPM_REG_DM(3),
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#define PRTDCB_TLPM_REG_DM(_i) (0x000A0000 + ((_i) * 4))
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PRTDCB_TLPM_REG_DM(0),
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PRTDCB_TLPM_REG_DM(1),
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PRTDCB_TLPM_REG_DM(2),
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PRTDCB_TLPM_REG_DM(3),
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};
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struct ice_priv_flag {
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