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ARM: shmobile: r8a7790: add EtherAVB clocks
Add the EtherAVB clock to the R8A7790 device tree. Based on original patch by Mitsuhiro Kimura <mitsuhiro.kimura.kc@renesas.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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2 changed files with 7 additions and 4 deletions
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@ -1249,16 +1249,18 @@
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compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
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compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
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reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
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clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
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clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
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<&zg_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>;
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<&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>,
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<&zs_clk>;
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#clock-cells = <1>;
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#clock-cells = <1>;
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clock-indices = <
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clock-indices = <
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R8A7790_CLK_MLB R8A7790_CLK_VIN3 R8A7790_CLK_VIN2
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R8A7790_CLK_MLB R8A7790_CLK_VIN3 R8A7790_CLK_VIN2
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R8A7790_CLK_VIN1 R8A7790_CLK_VIN0 R8A7790_CLK_ETHER
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R8A7790_CLK_VIN1 R8A7790_CLK_VIN0
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R8A7790_CLK_ETHERAVB R8A7790_CLK_ETHER
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R8A7790_CLK_SATA1 R8A7790_CLK_SATA0
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R8A7790_CLK_SATA1 R8A7790_CLK_SATA0
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>;
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>;
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clock-output-names =
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clock-output-names =
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"mlb", "vin3", "vin2", "vin1", "vin0", "ether",
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"mlb", "vin3", "vin2", "vin1", "vin0",
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"sata1", "sata0";
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"etheravb", "ether", "sata1", "sata0";
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};
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};
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mstp9_clks: mstp9_clks@e6150994 {
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mstp9_clks: mstp9_clks@e6150994 {
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compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
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compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
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@ -108,6 +108,7 @@
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#define R8A7790_CLK_VIN2 9
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#define R8A7790_CLK_VIN2 9
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#define R8A7790_CLK_VIN1 10
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#define R8A7790_CLK_VIN1 10
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#define R8A7790_CLK_VIN0 11
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#define R8A7790_CLK_VIN0 11
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#define R8A7790_CLK_ETHERAVB 12
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#define R8A7790_CLK_ETHER 13
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#define R8A7790_CLK_ETHER 13
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#define R8A7790_CLK_SATA1 14
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#define R8A7790_CLK_SATA1 14
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#define R8A7790_CLK_SATA0 15
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#define R8A7790_CLK_SATA0 15
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