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um: add PCI over virtio emulation driver

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To support testing of PCI/PCIe drivers in UML, add a PCI bus
support driver. This driver uses virtio, which in UML is really
just vhost-user, to talk to devices, and adds the devices to
the virtual PCI bus in the system.

Since virtio already allows DMA/bus mastering this really isn't
all that hard, of course we need the logic_iomem infrastructure
that was added by a previous patch.

The protocol to talk to the device is has a few fairly simple
messages for reading to/writing from config and IO spaces, and
messages for the device to send the various interrupts (INT#,
MSI/MSI-X and while suspended PME#).

Note that currently no offical virtio device ID is assigned for
this protocol, as a consequence this patch requires defining it
in the Kconfig, with a default that makes the driver refuse to
work at all.

Finally, in order to add support for MSI/MSI-X interrupts, some
small changes are needed in the UML IRQ code, it needs to have
more interrupts, changing NR_IRQS from 64 to 128 if this driver
is enabled, but not actually use them for anything so that the
generic IRQ domain/MSI infrastructure can allocate IRQ numbers.

Signed-off-by: Johannes Berg <johannes.berg@intel.com>
Signed-off-by: Richard Weinberger <richard@nod.at>
This commit is contained in:
Johannes Berg 2021-03-05 13:19:58 +01:00 • committed by Richard Weinberger
parent a5ab7c8467
commit 68f5d3f3b6
13 changed files with 1054 additions and 6 deletions
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64
include/uapi/linux/virtio_pcidev.h Normal file
View file

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/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */
/*
* Copyright (C) 2021 Intel Corporation
* Author: Johannes Berg <johannes@sipsolutions.net>
*/
#ifndef _UAPI_LINUX_VIRTIO_PCIDEV_H
#define _UAPI_LINUX_VIRTIO_PCIDEV_H
#include <linux/types.h>
/**
* enum virtio_pcidev_ops - virtual PCI device operations
* @VIRTIO_PCIDEV_OP_CFG_READ: read config space, size is 1, 2, 4 or 8;
* the @data field should be filled in by the device (in little endian).
* @VIRTIO_PCIDEV_OP_CFG_WRITE: write config space, size is 1, 2, 4 or 8;
* the @data field contains the data to write (in little endian).
* @VIRTIO_PCIDEV_OP_BAR_READ: read BAR mem/pio, size can be variable;
* the @data field should be filled in by the device (in little endian).
* @VIRTIO_PCIDEV_OP_BAR_WRITE: write BAR mem/pio, size can be variable;
* the @data field contains the data to write (in little endian).
* @VIRTIO_PCIDEV_OP_MMIO_MEMSET: memset MMIO, size is variable but
* the @data field only has one byte (unlike @VIRTIO_PCIDEV_OP_MMIO_WRITE)
* @VIRTIO_PCIDEV_OP_INT: legacy INTx# pin interrupt, the addr field is 1-4 for
* the number
* @VIRTIO_PCIDEV_OP_MSI: MSI(-X) interrupt, this message basically transports
* the 16- or 32-bit write that would otherwise be done into memory,
* analogous to the write messages (@VIRTIO_PCIDEV_OP_MMIO_WRITE) above
* @VIRTIO_PCIDEV_OP_PME: Dummy message whose content is ignored (and should be
* all zeroes) to signal the PME# pin.
*/
enum virtio_pcidev_ops {
VIRTIO_PCIDEV_OP_RESERVED = 0,
VIRTIO_PCIDEV_OP_CFG_READ,
VIRTIO_PCIDEV_OP_CFG_WRITE,
VIRTIO_PCIDEV_OP_MMIO_READ,
VIRTIO_PCIDEV_OP_MMIO_WRITE,
VIRTIO_PCIDEV_OP_MMIO_MEMSET,
VIRTIO_PCIDEV_OP_INT,
VIRTIO_PCIDEV_OP_MSI,
VIRTIO_PCIDEV_OP_PME,
};
/**
* struct virtio_pcidev_msg - virtio PCI device operation
* @op: the operation to do
* @bar: the bar (only with BAR read/write messages)
* @reserved: reserved
* @size: the size of the read/write (in bytes)
* @addr: the address to read/write
* @data: the data, normally @size long, but just one byte for
* %VIRTIO_PCIDEV_OP_MMIO_MEMSET
*
* Note: the fields are all in native (CPU) endian, however, the
* @data values will often be in little endian (see the ops above.)
*/
struct virtio_pcidev_msg {
__u8 op;
__u8 bar;
__u16 reserved;
__u32 size;
__u64 addr;
__u8 data[];
};
#endif /* _UAPI_LINUX_VIRTIO_PCIDEV_H */