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drm/amd/display: really fix time out in init sequence

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REG_UPDATE_2 return the reg value it write out through MMIO
we need to do a REG_READ to confirm the value is written out

Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Tony Cheng 2017-11-22 11:51:30 -05:00 • committed by Alex Deucher
parent a018298ff8
commit 75c2dec31a
1 changed files with 3 additions and 2 deletions
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5
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
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@ -42,13 +42,14 @@ void hubp1_set_blank(struct hubp *hubp, bool blank)
{ {
struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
uint32_t blank_en = blank ? 1 : 0; uint32_t blank_en = blank ? 1 : 0;
uint32_t reg_val = 0;
reg_val = REG_UPDATE_2(DCHUBP_CNTL, REG_UPDATE_2(DCHUBP_CNTL,
HUBP_BLANK_EN, blank_en, HUBP_BLANK_EN, blank_en,
HUBP_TTU_DISABLE, blank_en); HUBP_TTU_DISABLE, blank_en);
if (blank) { if (blank) {
uint32_t reg_val = REG_READ(DCHUBP_CNTL);
if (reg_val) { if (reg_val) {
/* init sequence workaround: in case HUBP is /* init sequence workaround: in case HUBP is
* power gated, this wait would timeout. * power gated, this wait would timeout.