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powerpc/booke64: Use SPRG_TLB_EXFRAME on bolted handlers

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While bolted handlers (including e6500) do not need to deal with a TLB
miss recursively causing another TLB miss, nested TLB misses can still
happen with crit/mc/debug exceptions -- so we still need to honor
SPRG_TLB_EXFRAME.

We don't need to spend time modifying it in the TLB miss fastpath,
though -- the special level exception will handle that.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Mihai Caraman <mihai.caraman@freescale.com>
Cc: kvm-ppc@vger.kernel.org
This commit is contained in:
Scott Wood 2014-03-10 17:29:38 -05:00
parent 9d378dfac8
commit a3dc620743
4 changed files with 42 additions and 31 deletions
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11
arch/powerpc/kvm/bookehv_interrupts.S
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@ -229,13 +229,20 @@
stw r10, VCPU_CR(r4)
PPC_STL r11, VCPU_GPR(R4)(r4)
PPC_STL r5, VCPU_GPR(R5)(r4)
mfspr r5, \scratch
PPC_STL r6, VCPU_GPR(R6)(r4)
PPC_STL r8, VCPU_GPR(R8)(r4)
PPC_STL r9, VCPU_GPR(R9)(r4)
PPC_STL r5, VCPU_GPR(R13)(r4)
.if \type == EX_TLB
PPC_LL r5, EX_TLB_R13(r12)
PPC_LL r6, EX_TLB_R10(r12)
PPC_LL r8, EX_TLB_R11(r12)
mfspr r12, \scratch
.else
mfspr r5, \scratch
PPC_LL r6, (\paca_ex + \ex_r10)(r13)
PPC_LL r8, (\paca_ex + \ex_r11)(r13)
.endif
PPC_STL r5, VCPU_GPR(R13)(r4)
PPC_STL r3, VCPU_GPR(R3)(r4)
PPC_STL r7, VCPU_GPR(R7)(r4)
PPC_STL r12, VCPU_GPR(R12)(r4)