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MIPS: MT: Remove SMTC support
Nobody is maintaining SMTC anymore and there also seems to be no userbase. Which is a pity - the SMTC technology primarily developed by Kevin D. Kissell <kevink@paralogos.com> is an ingenious demonstration for the MT ASE's power and elegance. Based on Markos Chandras <Markos.Chandras@imgtec.com> patch https://patchwork.linux-mips.org/patch/6719/ which while very similar did no longer apply cleanly when I tried to merge it plus some additional post-SMTC cleanup - SMTC was a feature as tricky to remove as it was to merge once upon a time. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle
parent
8b2e62cc34
commit
b633648c5a
64 changed files with 72 additions and 4097 deletions
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@ -19,22 +19,12 @@
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#include <asm/asm-offsets.h>
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#include <asm/thread_info.h>
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/*
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* For SMTC kernel, global IE should be left set, and interrupts
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* controlled exclusively via IXMT.
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*/
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#ifdef CONFIG_MIPS_MT_SMTC
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#define STATMASK 0x1e
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#elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
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#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
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#define STATMASK 0x3f
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#else
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#define STATMASK 0x1f
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#endif
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#ifdef CONFIG_MIPS_MT_SMTC
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#include <asm/mipsmtregs.h>
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#endif /* CONFIG_MIPS_MT_SMTC */
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.macro SAVE_AT
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.set push
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.set noat
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@ -186,16 +176,6 @@
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mfc0 v1, CP0_STATUS
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LONG_S $2, PT_R2(sp)
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LONG_S v1, PT_STATUS(sp)
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#ifdef CONFIG_MIPS_MT_SMTC
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/*
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* Ideally, these instructions would be shuffled in
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* to cover the pipeline delay.
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*/
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.set mips32
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mfc0 k0, CP0_TCSTATUS
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.set mips0
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LONG_S k0, PT_TCSTATUS(sp)
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#endif /* CONFIG_MIPS_MT_SMTC */
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LONG_S $4, PT_R4(sp)
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mfc0 v1, CP0_CAUSE
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LONG_S $5, PT_R5(sp)
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@ -321,36 +301,6 @@
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.set push
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.set reorder
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.set noat
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#ifdef CONFIG_MIPS_MT_SMTC
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.set mips32r2
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/*
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* We need to make sure the read-modify-write
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* of Status below isn't perturbed by an interrupt
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* or cross-TC access, so we need to do at least a DMT,
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* protected by an interrupt-inhibit. But setting IXMT
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* also creates a few-cycle window where an IPI could
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* be queued and not be detected before potentially
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* returning to a WAIT or user-mode loop. It must be
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* replayed.
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*
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* We're in the middle of a context switch, and
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* we can't dispatch it directly without trashing
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* some registers, so we'll try to detect this unlikely
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* case and program a software interrupt in the VPE,
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* as would be done for a cross-VPE IPI. To accommodate
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* the handling of that case, we're doing a DVPE instead
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* of just a DMT here to protect against other threads.
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* This is a lot of cruft to cover a tiny window.
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* If you can find a better design, implement it!
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*
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*/
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mfc0 v0, CP0_TCSTATUS
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ori v0, TCSTATUS_IXMT
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mtc0 v0, CP0_TCSTATUS
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_ehb
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DVPE 5 # dvpe a1
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jal mips_ihb
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#endif /* CONFIG_MIPS_MT_SMTC */
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mfc0 a0, CP0_STATUS
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ori a0, STATMASK
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xori a0, STATMASK
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@ -362,59 +312,6 @@
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and v0, v1
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or v0, a0
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mtc0 v0, CP0_STATUS
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#ifdef CONFIG_MIPS_MT_SMTC
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/*
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* Only after EXL/ERL have been restored to status can we
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* restore TCStatus.IXMT.
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*/
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LONG_L v1, PT_TCSTATUS(sp)
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_ehb
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mfc0 a0, CP0_TCSTATUS
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andi v1, TCSTATUS_IXMT
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bnez v1, 0f
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/*
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* We'd like to detect any IPIs queued in the tiny window
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* above and request an software interrupt to service them
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* when we ERET.
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*
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* Computing the offset into the IPIQ array of the executing
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* TC's IPI queue in-line would be tedious. We use part of
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* the TCContext register to hold 16 bits of offset that we
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* can add in-line to find the queue head.
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*/
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mfc0 v0, CP0_TCCONTEXT
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la a2, IPIQ
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srl v0, v0, 16
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addu a2, a2, v0
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LONG_L v0, 0(a2)
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beqz v0, 0f
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/*
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* If we have a queue, provoke dispatch within the VPE by setting C_SW1
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*/
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mfc0 v0, CP0_CAUSE
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ori v0, v0, C_SW1
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mtc0 v0, CP0_CAUSE
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0:
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/*
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* This test should really never branch but
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* let's be prudent here. Having atomized
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* the shared register modifications, we can
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* now EVPE, and must do so before interrupts
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* are potentially re-enabled.
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*/
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andi a1, a1, MVPCONTROL_EVP
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beqz a1, 1f
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evpe
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1:
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/* We know that TCStatua.IXMT should be set from above */
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xori a0, a0, TCSTATUS_IXMT
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or a0, a0, v1
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mtc0 a0, CP0_TCSTATUS
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_ehb
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.set mips0
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#endif /* CONFIG_MIPS_MT_SMTC */
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LONG_L v1, PT_EPC(sp)
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MTC0 v1, CP0_EPC
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LONG_L $31, PT_R31(sp)
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@ -467,33 +364,11 @@
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* Set cp0 enable bit as sign that we're running on the kernel stack
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*/
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.macro CLI
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#if !defined(CONFIG_MIPS_MT_SMTC)
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mfc0 t0, CP0_STATUS
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li t1, ST0_CU0 | STATMASK
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or t0, t1
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xori t0, STATMASK
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mtc0 t0, CP0_STATUS
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#else /* CONFIG_MIPS_MT_SMTC */
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/*
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* For SMTC, we need to set privilege
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* and disable interrupts only for the
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* current TC, using the TCStatus register.
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*/
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mfc0 t0, CP0_TCSTATUS
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/* Fortunately CU 0 is in the same place in both registers */
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/* Set TCU0, TMX, TKSU (for later inversion) and IXMT */
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li t1, ST0_CU0 | 0x08001c00
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or t0, t1
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/* Clear TKSU, leave IXMT */
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xori t0, 0x00001800
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mtc0 t0, CP0_TCSTATUS
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_ehb
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/* We need to leave the global IE bit set, but clear EXL...*/
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mfc0 t0, CP0_STATUS
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ori t0, ST0_EXL | ST0_ERL
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xori t0, ST0_EXL | ST0_ERL
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mtc0 t0, CP0_STATUS
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#endif /* CONFIG_MIPS_MT_SMTC */
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irq_disable_hazard
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.endm
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@ -502,35 +377,11 @@
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* Set cp0 enable bit as sign that we're running on the kernel stack
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*/
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.macro STI
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#if !defined(CONFIG_MIPS_MT_SMTC)
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mfc0 t0, CP0_STATUS
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li t1, ST0_CU0 | STATMASK
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or t0, t1
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xori t0, STATMASK & ~1
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mtc0 t0, CP0_STATUS
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#else /* CONFIG_MIPS_MT_SMTC */
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/*
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* For SMTC, we need to set privilege
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* and enable interrupts only for the
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* current TC, using the TCStatus register.
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*/
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_ehb
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mfc0 t0, CP0_TCSTATUS
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/* Fortunately CU 0 is in the same place in both registers */
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/* Set TCU0, TKSU (for later inversion) and IXMT */
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li t1, ST0_CU0 | 0x08001c00
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or t0, t1
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/* Clear TKSU *and* IXMT */
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xori t0, 0x00001c00
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mtc0 t0, CP0_TCSTATUS
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_ehb
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/* We need to leave the global IE bit set, but clear EXL...*/
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mfc0 t0, CP0_STATUS
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ori t0, ST0_EXL
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xori t0, ST0_EXL
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mtc0 t0, CP0_STATUS
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/* irq_enable_hazard below should expand to EHB for 24K/34K cpus */
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#endif /* CONFIG_MIPS_MT_SMTC */
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irq_enable_hazard
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.endm
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@ -540,32 +391,6 @@
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* Set cp0 enable bit as sign that we're running on the kernel stack
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*/
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.macro KMODE
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#ifdef CONFIG_MIPS_MT_SMTC
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/*
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* This gets baroque in SMTC. We want to
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* protect the non-atomic clearing of EXL
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* with DMT/EMT, but we don't want to take
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* an interrupt while DMT is still in effect.
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*/
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/* KMODE gets invoked from both reorder and noreorder code */
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.set push
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.set mips32r2
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.set noreorder
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mfc0 v0, CP0_TCSTATUS
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andi v1, v0, TCSTATUS_IXMT
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ori v0, TCSTATUS_IXMT
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mtc0 v0, CP0_TCSTATUS
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_ehb
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DMT 2 # dmt v0
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/*
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* We don't know a priori if ra is "live"
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*/
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move t0, ra
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jal mips_ihb
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nop /* delay slot */
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move ra, t0
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#endif /* CONFIG_MIPS_MT_SMTC */
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mfc0 t0, CP0_STATUS
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li t1, ST0_CU0 | (STATMASK & ~1)
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#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
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@ -576,25 +401,6 @@
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or t0, t1
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xori t0, STATMASK & ~1
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mtc0 t0, CP0_STATUS
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#ifdef CONFIG_MIPS_MT_SMTC
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_ehb
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andi v0, v0, VPECONTROL_TE
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beqz v0, 2f
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nop /* delay slot */
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emt
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2:
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mfc0 v0, CP0_TCSTATUS
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/* Clear IXMT, then OR in previous value */
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ori v0, TCSTATUS_IXMT
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xori v0, TCSTATUS_IXMT
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or v0, v1, v0
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mtc0 v0, CP0_TCSTATUS
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/*
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* irq_disable_hazard below should expand to EHB
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* on 24K/34K CPUS
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*/
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.set pop
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#endif /* CONFIG_MIPS_MT_SMTC */
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irq_disable_hazard
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.endm
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