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MIPS: Remove unused R5432_CP0_INTERRUPT_WAR

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R5432_CP0_INTERRUPT_WAR is defined as 0 for every system we support, and
so the workaround is never used. Remove the dead code.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
This commit is contained in:
Paul Burton 2019-07-22 22:00:00 +00:00
parent 8e96b08472
commit ccd51b9fc3
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14 changed files with 0 additions and 28 deletions
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13
arch/mips/include/asm/war.h
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@ -128,19 +128,6 @@
#error Check setting of R4600_V2_HIT_CACHEOP_WAR for your platform
#endif
/*
* When an interrupt happens on a CP0 register read instruction, CPU may
* lock up or read corrupted values of CP0 registers after it enters
* the exception handler.
*
* This workaround makes sure that we read a "safe" CP0 register as the
* first thing in the exception handler, which breaks one of the
* pre-conditions for this problem.
*/
#ifndef R5432_CP0_INTERRUPT_WAR
#error Check setting of R5432_CP0_INTERRUPT_WAR for your platform
#endif
/*
* Workaround for the Sibyte M3 errata the text of which can be found at
*