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powerpc/virtex: Fix booting of Xilinx FPGAs with 16550 for 405 and 440

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The following changes add processing to initialize the Xilinx 16550 UART
in the boot wrapper for Virtex targets without firmware.  Normally the
boot wrapper assumes that the serial port has already been initialized by
firmware.

The wrapper was also modified to add the 440 build.

Signed-off-by: John Linn <john.linn@xilinx.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
This commit is contained in:
John Linn 2008-07-02 15:11:28 -07:00 • committed by Grant Likely
parent dc568ec490
commit d58577d8f3
4 changed files with 112 additions and 2 deletions
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6
arch/powerpc/boot/simpleboot.c
View file

@ -23,6 +23,8 @@
BSS_STACK(4*1024);
extern int platform_specific_init(void) __attribute__((weak));
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
{
@ -80,5 +82,9 @@ void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
/* prepare the device tree and find the console */
fdt_init(_dtb_start);
if (platform_specific_init)
platform_specific_init();
serial_console_init();
}