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https://github.com/Fishwaldo/linux-bl808.git
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Merge branch 'bnxt_en-updates'
Michael Chan says: ==================== bnxt_en: Updates This small patchset adds an improvement to the configuration of ethtool RSS tuple hash and a PTP improvement when running in a multi-host environment. ==================== Link: https://lore.kernel.org/r/1667780192-3700-1-git-send-email-michael.chan@broadcom.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
This commit is contained in:
commit
ee1bfbcc71
6 changed files with 142 additions and 33 deletions
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@ -5250,7 +5250,7 @@ int bnxt_get_nr_rss_ctxs(struct bnxt *bp, int rx_rings)
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return 1;
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}
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static void __bnxt_fill_hw_rss_tbl(struct bnxt *bp, struct bnxt_vnic_info *vnic)
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static void bnxt_fill_hw_rss_tbl(struct bnxt *bp, struct bnxt_vnic_info *vnic)
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{
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bool no_rss = !(vnic->flags & BNXT_VNIC_RSS_FLAG);
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u16 i, j;
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@ -5263,8 +5263,8 @@ static void __bnxt_fill_hw_rss_tbl(struct bnxt *bp, struct bnxt_vnic_info *vnic)
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}
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}
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static void __bnxt_fill_hw_rss_tbl_p5(struct bnxt *bp,
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struct bnxt_vnic_info *vnic)
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static void bnxt_fill_hw_rss_tbl_p5(struct bnxt *bp,
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struct bnxt_vnic_info *vnic)
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{
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__le16 *ring_tbl = vnic->rss_table;
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struct bnxt_rx_ring_info *rxr;
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@ -5285,12 +5285,27 @@ static void __bnxt_fill_hw_rss_tbl_p5(struct bnxt *bp,
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}
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}
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static void bnxt_fill_hw_rss_tbl(struct bnxt *bp, struct bnxt_vnic_info *vnic)
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static void
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__bnxt_hwrm_vnic_set_rss(struct bnxt *bp, struct hwrm_vnic_rss_cfg_input *req,
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struct bnxt_vnic_info *vnic)
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{
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if (bp->flags & BNXT_FLAG_CHIP_P5)
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__bnxt_fill_hw_rss_tbl_p5(bp, vnic);
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bnxt_fill_hw_rss_tbl_p5(bp, vnic);
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else
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__bnxt_fill_hw_rss_tbl(bp, vnic);
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bnxt_fill_hw_rss_tbl(bp, vnic);
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if (bp->rss_hash_delta) {
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req->hash_type = cpu_to_le32(bp->rss_hash_delta);
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if (bp->rss_hash_cfg & bp->rss_hash_delta)
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req->flags |= VNIC_RSS_CFG_REQ_FLAGS_HASH_TYPE_INCLUDE;
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else
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req->flags |= VNIC_RSS_CFG_REQ_FLAGS_HASH_TYPE_EXCLUDE;
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} else {
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req->hash_type = cpu_to_le32(bp->rss_hash_cfg);
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}
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req->hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT;
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req->ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
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req->hash_key_tbl_addr = cpu_to_le64(vnic->rss_hash_key_dma_addr);
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}
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static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
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@ -5307,14 +5322,8 @@ static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
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if (rc)
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return rc;
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if (set_rss) {
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bnxt_fill_hw_rss_tbl(bp, vnic);
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req->hash_type = cpu_to_le32(bp->rss_hash_cfg);
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req->hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT;
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req->ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
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req->hash_key_tbl_addr =
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cpu_to_le64(vnic->rss_hash_key_dma_addr);
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}
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if (set_rss)
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__bnxt_hwrm_vnic_set_rss(bp, req, vnic);
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req->rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
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return hwrm_req_send(bp, req);
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}
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@ -5335,10 +5344,7 @@ static int bnxt_hwrm_vnic_set_rss_p5(struct bnxt *bp, u16 vnic_id, bool set_rss)
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if (!set_rss)
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return hwrm_req_send(bp, req);
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bnxt_fill_hw_rss_tbl(bp, vnic);
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req->hash_type = cpu_to_le32(bp->rss_hash_cfg);
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req->hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT;
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req->hash_key_tbl_addr = cpu_to_le64(vnic->rss_hash_key_dma_addr);
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__bnxt_hwrm_vnic_set_rss(bp, req, vnic);
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ring_tbl_map = vnic->rss_table_dma_addr;
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nr_ctxs = bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings);
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@ -5357,6 +5363,25 @@ exit:
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return rc;
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}
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static void bnxt_hwrm_update_rss_hash_cfg(struct bnxt *bp)
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{
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struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
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struct hwrm_vnic_rss_qcfg_output *resp;
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struct hwrm_vnic_rss_qcfg_input *req;
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if (hwrm_req_init(bp, req, HWRM_VNIC_RSS_QCFG))
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return;
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/* all contexts configured to same hash_type, zero always exists */
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req->rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
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resp = hwrm_req_hold(bp, req);
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if (!hwrm_req_send(bp, req)) {
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bp->rss_hash_cfg = le32_to_cpu(resp->hash_type) ?: bp->rss_hash_cfg;
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bp->rss_hash_delta = 0;
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}
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hwrm_req_drop(bp, req);
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}
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static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
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{
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struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
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@ -5614,6 +5639,8 @@ static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
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(BNXT_CHIP_P5_THOR(bp) &&
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!(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED)))
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bp->fw_cap |= BNXT_FW_CAP_VLAN_RX_STRIP;
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if (flags & VNIC_QCAPS_RESP_FLAGS_RSS_HASH_TYPE_DELTA_CAP)
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bp->fw_cap |= BNXT_FW_CAP_RSS_HASH_TYPE_DELTA;
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bp->max_tpa_v2 = le16_to_cpu(resp->max_aggs_supported);
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if (bp->max_tpa_v2) {
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if (BNXT_CHIP_P5_THOR(bp))
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@ -6958,8 +6985,11 @@ static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
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if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED)
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bp->fw_cap |= BNXT_FW_CAP_DCBX_AGENT;
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}
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if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST))
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if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST)) {
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bp->flags |= BNXT_FLAG_MULTI_HOST;
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if (bp->fw_cap & BNXT_FW_CAP_PTP_RTC)
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bp->fw_cap &= ~BNXT_FW_CAP_PTP_RTC;
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}
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if (flags & FUNC_QCFG_RESP_FLAGS_RING_MONITOR_ENABLED)
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bp->fw_cap |= BNXT_FW_CAP_RING_MONITOR;
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@ -8808,6 +8838,8 @@ static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
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rc = bnxt_setup_vnic(bp, 0);
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if (rc)
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goto err_out;
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if (bp->fw_cap & BNXT_FW_CAP_RSS_HASH_TYPE_DELTA)
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bnxt_hwrm_update_rss_hash_cfg(bp);
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if (bp->flags & BNXT_FLAG_RFS) {
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rc = bnxt_alloc_rfs_vnics(bp);
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@ -12243,6 +12275,8 @@ static void bnxt_set_dflt_rss_hash_type(struct bnxt *bp)
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VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 |
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VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 |
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VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
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if (bp->fw_cap & BNXT_FW_CAP_RSS_HASH_TYPE_DELTA)
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bp->rss_hash_delta = bp->rss_hash_cfg;
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if (BNXT_CHIP_P4_PLUS(bp) && bp->hwrm_spec_code >= 0x10501) {
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bp->flags |= BNXT_FLAG_UDP_RSS_CAP;
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bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 |
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@ -1900,6 +1900,7 @@ struct bnxt {
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u16 *rss_indir_tbl;
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u16 rss_indir_tbl_entries;
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u32 rss_hash_cfg;
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u32 rss_hash_delta;
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u16 max_mtu;
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u8 max_tc;
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@ -1965,6 +1966,7 @@ struct bnxt {
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#define BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2 0x00010000
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#define BNXT_FW_CAP_PCIE_STATS_SUPPORTED 0x00020000
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#define BNXT_FW_CAP_EXT_STATS_SUPPORTED 0x00040000
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#define BNXT_FW_CAP_RSS_HASH_TYPE_DELTA 0x00080000
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#define BNXT_FW_CAP_ERR_RECOVER_RELOAD 0x00100000
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#define BNXT_FW_CAP_HOT_RESET 0x00200000
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#define BNXT_FW_CAP_PTP_RTC 0x00400000
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@ -1234,6 +1234,8 @@ static int bnxt_srxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd)
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if (bp->rss_hash_cfg == rss_hash_cfg)
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return 0;
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if (bp->fw_cap & BNXT_FW_CAP_RSS_HASH_TYPE_DELTA)
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bp->rss_hash_delta = bp->rss_hash_cfg ^ rss_hash_cfg;
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bp->rss_hash_cfg = rss_hash_cfg;
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if (netif_running(bp->dev)) {
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bnxt_close_nic(bp, false, false);
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@ -6768,6 +6768,53 @@ struct hwrm_vnic_rss_cfg_cmd_err {
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u8 unused_0[7];
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};
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/* hwrm_vnic_rss_qcfg_input (size:192b/24B) */
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struct hwrm_vnic_rss_qcfg_input {
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__le16 req_type;
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__le16 cmpl_ring;
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__le16 seq_id;
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__le16 target_id;
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__le64 resp_addr;
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__le16 rss_ctx_idx;
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__le16 vnic_id;
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u8 unused_0[4];
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};
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/* hwrm_vnic_rss_qcfg_output (size:512b/64B) */
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struct hwrm_vnic_rss_qcfg_output {
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__le16 error_code;
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__le16 req_type;
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__le16 seq_id;
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__le16 resp_len;
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__le32 hash_type;
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#define VNIC_RSS_QCFG_RESP_HASH_TYPE_IPV4 0x1UL
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#define VNIC_RSS_QCFG_RESP_HASH_TYPE_TCP_IPV4 0x2UL
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#define VNIC_RSS_QCFG_RESP_HASH_TYPE_UDP_IPV4 0x4UL
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#define VNIC_RSS_QCFG_RESP_HASH_TYPE_IPV6 0x8UL
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#define VNIC_RSS_QCFG_RESP_HASH_TYPE_TCP_IPV6 0x10UL
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#define VNIC_RSS_QCFG_RESP_HASH_TYPE_UDP_IPV6 0x20UL
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#define VNIC_RSS_QCFG_RESP_HASH_TYPE_IPV6_FLOW_LABEL 0x40UL
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#define VNIC_RSS_QCFG_RESP_HASH_TYPE_AH_SPI_IPV4 0x80UL
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#define VNIC_RSS_QCFG_RESP_HASH_TYPE_ESP_SPI_IPV4 0x100UL
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#define VNIC_RSS_QCFG_RESP_HASH_TYPE_AH_SPI_IPV6 0x200UL
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#define VNIC_RSS_QCFG_RESP_HASH_TYPE_ESP_SPI_IPV6 0x400UL
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u8 unused_0[4];
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__le32 hash_key[10];
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u8 hash_mode_flags;
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#define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_DEFAULT 0x1UL
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#define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_INNERMOST_4 0x2UL
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#define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_INNERMOST_2 0x4UL
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#define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_OUTERMOST_4 0x8UL
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#define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_OUTERMOST_2 0x10UL
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u8 ring_select_mode;
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#define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_TOEPLITZ 0x0UL
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#define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_XOR 0x1UL
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#define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_TOEPLITZ_CHECKSUM 0x2UL
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#define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_LAST VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_TOEPLITZ_CHECKSUM
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u8 unused_1[5];
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u8 valid;
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};
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/* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */
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struct hwrm_vnic_plcmodes_cfg_input {
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__le16 req_type;
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@ -14,6 +14,7 @@
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#include <linux/net_tstamp.h>
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#include <linux/timekeeping.h>
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#include <linux/ptp_classify.h>
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#include <linux/clocksource.h>
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#include "bnxt_hsi.h"
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#include "bnxt.h"
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#include "bnxt_hwrm.h"
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@ -210,18 +211,37 @@ static int bnxt_ptp_adjfreq(struct ptp_clock_info *ptp_info, s32 ppb)
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ptp_info);
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struct hwrm_port_mac_cfg_input *req;
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struct bnxt *bp = ptp->bp;
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int rc;
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int rc = 0;
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rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG);
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if (rc)
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return rc;
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if (!(ptp->bp->fw_cap & BNXT_FW_CAP_PTP_RTC)) {
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int neg_adj = 0;
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u32 diff;
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u64 adj;
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req->ptp_freq_adj_ppb = cpu_to_le32(ppb);
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req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB);
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rc = hwrm_req_send(ptp->bp, req);
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if (rc)
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netdev_err(ptp->bp->dev,
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"ptp adjfreq failed. rc = %d\n", rc);
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if (ppb < 0) {
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neg_adj = 1;
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ppb = -ppb;
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}
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adj = ptp->cmult;
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adj *= ppb;
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diff = div_u64(adj, 1000000000ULL);
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spin_lock_bh(&ptp->ptp_lock);
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timecounter_read(&ptp->tc);
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ptp->cc.mult = neg_adj ? ptp->cmult - diff : ptp->cmult + diff;
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spin_unlock_bh(&ptp->ptp_lock);
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} else {
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rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG);
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if (rc)
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return rc;
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req->ptp_freq_adj_ppb = cpu_to_le32(ppb);
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req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB);
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rc = hwrm_req_send(ptp->bp, req);
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if (rc)
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netdev_err(ptp->bp->dev,
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"ptp adjfreq failed. rc = %d\n", rc);
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}
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return rc;
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}
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@ -846,8 +866,9 @@ static void bnxt_ptp_timecounter_init(struct bnxt *bp, bool init_tc)
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memset(&ptp->cc, 0, sizeof(ptp->cc));
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ptp->cc.read = bnxt_cc_read;
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ptp->cc.mask = CYCLECOUNTER_MASK(48);
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ptp->cc.shift = 0;
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ptp->cc.mult = 1;
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ptp->cc.shift = BNXT_CYCLES_SHIFT;
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ptp->cc.mult = clocksource_khz2mult(BNXT_DEVCLK_FREQ, ptp->cc.shift);
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ptp->cmult = ptp->cc.mult;
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ptp->next_overflow_check = jiffies + BNXT_PHC_OVERFLOW_PERIOD;
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}
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if (init_tc)
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@ -17,6 +17,8 @@
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#define BNXT_PTP_GRC_WIN_BASE 0x6000
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#define BNXT_MAX_PHC_DRIFT 31000000
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#define BNXT_CYCLES_SHIFT 23
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#define BNXT_DEVCLK_FREQ 1000000
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#define BNXT_LO_TIMER_MASK 0x0000ffffffffUL
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#define BNXT_HI_TIMER_MASK 0xffff00000000UL
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@ -88,8 +90,9 @@ struct bnxt_ptp_cfg {
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u64 old_time;
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unsigned long next_period;
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unsigned long next_overflow_check;
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/* 48-bit PHC overflows in 78 hours. Check overflow every 19 hours. */
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#define BNXT_PHC_OVERFLOW_PERIOD (19 * 3600 * HZ)
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u32 cmult;
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/* a 23b shift cyclecounter will overflow in ~36 mins. Check overflow every 18 mins. */
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#define BNXT_PHC_OVERFLOW_PERIOD (18 * 60 * HZ)
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u16 tx_seqid;
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u16 tx_hdr_off;
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