This adds an entry to the uart_config table for PORT_RT2880
enabling rx/tx FIFOs. The UART is actually a Palmchip BK-3103
which is found in several devices from Alchemy/RMI, Ralink, and
Sigma Designs.
Signed-off-by: Mans Rullgard <mans@mansr.com>
Cc: stable <stable@vger.kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
The split of the 8250 driver into a 8250_base/8250.ko resulted in a
lack of a license for the 8250_base.ko module. This caused the module
to fail to load and the kernel to be tainted. Add the appropriate
MODULE_LICENSE to 8250_port.c, which is always compiled into
8250_base.ko
Signed-off-by: Jonathan McDowell <noodles@earth.li>
Reported-by: Mikael Pettersson <mikpelinux@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
The XR17V35X UART needs the ECB bit set in its XR_EFR
register to enable access to IER [7:5], ISR [5:4], FCR[5:4],
MCR[7:5], and MSR [7:0].
Also reset the IER register to mask interrupts after access
to all bits of this register has been enabled.
This makes my 8-port XR17V35X working with the in-kernel
serial driver.
Cc: Joe Schultz <jschultz@xes-inc.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Reviewed-by: Peter Hurley <peter@hurleysoftware.com>
Reviewed-by: Michael Welling <mwelling@ieee.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
An already-active sender can swamp the interrupt handler with
"too much work" if the rx interrupts are enabled when the fifo is
disabled and operating in single-byte mode.
Defer rx and line status interrupt enable until after the fifos
are enabled in set_termios(), but at least initialize the shadow
IER value with the interrupts which will be enabled.
Signed-off-by: Peter Hurley <peter@hurleysoftware.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
