Tony Luck e464121f2d x86/cpu: Add Xeon Icelake-D to list of CPUs that support PPIN ... Missed adding the Icelake-D CPU to the list. It uses the same MSRs to control and read the inventory number as all the other models. Fixes: dc6b025de9 ("x86/mce: Add Xeon Icelake to list of CPUs that support PPIN") Reported-by: Ailin Xu <ailin.xu@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Borislav Petkov <bp@suse.de> Cc: <stable@vger.kernel.org> Link: https://lore.kernel.org/r/20220121174743.1875294-2-tony.luck@intel.com		2022-01-25 18:40:30 +01:00
..
amd.c	x86/MCE/AMD: Allow thresholding interface updates after init	2022-01-23 20:50:18 +01:00
apei.c
core.c	x86/mce: Mark mce_start() noinstr	2021-12-13 14:14:05 +01:00
dev-mcelog.c
genpool.c
inject.c	x86/mce/inject: Avoid out-of-bounds write when setting flags	2021-12-28 11:45:36 +01:00
intel.c	x86/cpu: Add Xeon Icelake-D to list of CPUs that support PPIN	2022-01-25 18:40:30 +01:00
internal.h	x86/mce: Use mce_rdmsrl() in severity checking code	2021-12-13 14:12:08 +01:00
Makefile
p5.c
severity.c	x86/mce: Check regs before accessing it	2021-12-20 11:41:02 +01:00
threshold.c
winchip.c